Is the DMA overstrained? DMA & InputCapture Issues

[ColaChugger]

Hi everyone,

my setting looks like this:

CPU CLK: 480MHz

AHB CLK should be 240MHz (I'm not 100% sure)

Timer CLK 120MHz

InputCapture Channel: 4 (2 direct, 2 indirect)

I generate 8 short pulses each about 30ns. I use 4 InputCaptures to read those pulses. 2 InputCaptures for the rising edge and 2 InputCapture for the falling edge (falling edge configured as indirect mode). I use the DMA to get the values from the CCR and transfer them to an array. However it seems like the DMA can't handle this. Most of the time I get right values for 3 out of 4 streams. The last stream only gets 1 or 2 values out of 8.

The timer is supposed to run at 120MHz, the CPU at 480MHz and the DMA at 240MHz.

Can someone tell me if I'm doing something wrong? Is there something I overlooked? I tried FIFO mode and direct mode and got about similar results. I also tried fiddleing with the priorities and still got some wrong results.

Edit:

Sometimes no overcapture is detected although the data clearly indicates the opposite. Can someone explain?

Edit2: How come the DMA copies the same value twice into my array?

[waclawek.jan]

DMA together with the bus system it operates on, have their limits.

Have you read AN4031?

JW

[ColaChugger]

I assume you mean AN4013 (Cross timer overview) ? I did read it. However I did not find the information I was looking for. But I'm still a beginner, so I thought I missed/overlooked the information I need somewhere.

Apparently I did push the H7 to its limits. I lengthened the pulses a bit and got no errors anymore. But this is just a testing scenario. Now I have to find a reasonable solution for signals that are faster than my generated one.