Is it possible to use USB HUB with STM32F4 using external PHY?

[RhSilicon]

Hi, I found a post by Renesas, about using Azure rtos, where it is possible to use the HUB class for USB Host.

Can any problem already known to the internal PHY also occur in the external PHY? Is the external PHY able to be used with USB HUB?

Using Hub

• When the user uses the following device class, the user can use USB Hub.
  • Host Communication Device Class (HCDC)
  • Host Human Interface Device Class (HHID)
  • Host Mass Storage Class (HMSC)
  • Host Printer Class (HPRN)
• Also be sure to set the pipe number to the following items. Can not specify "NO USE" to the following items when using Hub.
  • Bulk In Pipe 2
  • Bulk Out Pipe 2
  • Interrupt In Pipe 2
  • Interrupt In PIpe 3

Note

• Please ignore the suspend or resume event occurs when attaching or detaching the USB cable.
• The following are notes on using the ux_host_class_cdc_acm_read function or the ux_device_class_cdc_acm_read function
  • Please specify a multiple of MaxPacketSize to the 3rd argument(requested_length) since if the value of the 3rd argument is not multiple of MaxPacketSize, all data sent by USB Host or USB Peripheral may not be received correctly.
  • Please specify start address of the area allocated a size larger than 3rd argument(requested_length) to the 2nd argument(data_pointer or buffer).
• There is no stack for the Hub; please select the stack for USB Host even when using the Hub.
• Depending on the Hub used, it may be necessary to supply power to the Hub.
• HUVC does not support USB Hub.

https://renesas.github.io/fsp/group___u_s_b_x.html

[STOne-32 · Accepted solution]

Dear @RhSilicon ,

we have many customers using STM32F4 as USB host and connecting a HUB using partners Hub class, the only known limitation at the internal PHY Full speed is to not connect a Low speed device as specified in the silicon errata here .

 However if an external ULPI PHY is used for High and full  speed it is working fine.

Hole it helps You.

STOne-32

[RhSilicon]

Won't increasing the capacitance of the data lines stress the silicon chip? How much is the value of the capacitor to be added in each line?