Hi @Bouraoui Chemli
Thanks for your quick answer! Any suggest about managging at app level each FIFO's reading separatedly or finding which mailbox generated the interrupt?
I've got further questions:
- Do I need to use CAN_Receive block with CAN_Read associated to same FIFO when enabling interrupts?
- How does my defined interrupt routine's execution works? In case that a new interrupt occurs while the routine is being executed because there is an incoming message at one mailbox:
- it waits until the excution is finished and right after the routine is executed by the second interruption,
- the next interrupt routine caused by the second interruption is lost
- or it stops current execution and starts new interrupt routine?
- When the interruption is generated, does it empty the mailbox from pending message or does it only serves first message pending at the FIFO?
- How much robust is the interrupt management? The generated code ensures that routine is executed without new interrupts? Or depends on the NVIC priorities settled on the .ioc file at CubeMX? Should I give maximum priority to CAN RX interrupt to ensure robustness and lossless reception?
I've search on Reference manual of my MCU but I haven't clarified all these doubts consistenly. Mainly because I don't know how HAL libraries are used by the block's generated code exactly.
