Invoking added performance using dual core

[fsonnichsen]

I have been driving CCD/CMOS linear arrays using PIC24s and have exceeded this processors 64mHz capability so i am seeking something much faster. I see that the STM32H7 MCU has a 480mHz clock and thought I would give it a try.

It is a little unclear to me when dealing with Dual Core MCUs whether the expressed clock rate per core is actually half that?

Also how does one know if there is any advantage using the dual core. I will be attempting to put a PWM on a GPIO at up to 2mHz and reading an internal ADC at that rate while storing the ADC data to an array. This is a fairly sequential/synchronous process of course.

Thanks--Fritz

[waclawek.jan]

> It is a little unclear to me when dealing with Dual Core MCUs whether the expressed clock rate per core is actually half that?

There's no magical split of workload in the "dual core" MCUs. They are simply two mcus built on one piece of silicon, sharing some of the resources. Omit the marketing material and go to the respective datasheet, it should be pretty clear in what are the capabilities ("megahertzs") for each mcu.

> put a PWM on a GPIO at up to 2mHz

Two millihertzs? That should be easy to accomplish.

ADCs can be triggered from timers, which output the PWM, or timers coupled to them; and the AD conversion result can be transferred to RAM using DMA. This all autonomously in hardware, without software involvement, i.e. for this process alone you wouldn't need high computing power of the core. If there's no other requirement for significant processing power, then you might then perhaps consider using some of the mid-range STM32, e.g. STM32F4, for reasons of cost, ease of programming, power consumption, thermal handling, lifetime.

You may want to start with some of the evaluation boards, Nucleo or Disco.

JW

[fsonnichsen]

Thanks Jan.

That was meant to be 2 Megahertz (not millihertz)

This is all valuable information. I played with and F4 Nucleo a few years back and will dig it out and start coding

cheers

fritz

[Tesla DeLorean]

Both the M7 (480 MHz) and M4 (240 MHz) cores can access the peripherals, you have to decide which you really want to manage them, and for the most part they live in the same bus domain as the M4 (240/120 MHz), so perhaps best to part IO tasks there. The peripheral and interrupt space maps to both processor cores.

Generally you're not going to want to be interrupting in the 2 MHz, the TIM can obviously manage themselves at this rate, but you'd want to decimate interrupt loading via DMA, or letting the TIM operate on a continuous/autonomous mode, modulating ARR or CCRx if need be.