Interfacing with memory mapped device (i.e. FPGA) on STM32F7 FMC bus

[jerry_sandc]

Hello all,

We're having some 'strange behaviour' when interfacing our STM32F7 to a FPGA over the FMC bus.  To isolate the problems, we're looking at all the control/addr/data on the FMC bus during memory transactions.  We have a very good view into everything via the Lattice Reveal tool.   The FPGA has 16-bit data bus, and we only want to access one register/memory location at a time.  

1. Even though we disabled data cache, we see multiple reads (separate NEx chip select assertions)
2. We are not using the MPU (yet)
3. We configured the FMC for 16-bit access, so it would ignore the upper halfword of the data bus.  We figured if we read only 16-bits, it would just do one read cycle (NEx assertion, OE assertion).  We see the memory controller trying to read address 0x00 and 0x01 in on read cycle, obviously 32-bits.   Our assembly code clearly shows ldrh (load data register half-word). 

Any insight welcome.  If you want us to post more detail, please ask.  Thanks all!!

[SofLit · Accepted solution]

Hello,

And what if you configure that memory region as Device attribute using MPU? What happens? 

[jerry_sandc]

After using MPU to setup region with all features disabled, it acts normally now.  We can read single 16-bit address now.  But please note there is no 'Device' attribute, we just disable all cache permissions, instruction access, etc.

[SofLit]

There is no implicit/direct confing for Device attribute:

MPU attributes are defined by their settings (as you did).

What you set is the Strongly-Ordered attribute would also solve the problem as Device attribute.

See this table from the AN4838.

[Pavel A.]

@SofLit So in context of this question, what is better: "shared device" (TEX=0) or "non-shareable device" (TEX=2) ?