in STM32G474 , Increasing the PLL frequency to 160Mhz (max allowable) make the core lock up and the core frequency can be increead to 160MHz only if AHB is prescaled

[gbm]

Check internal power supply settings and Flash wait states.

[AIBRA.1]

I performed these steps appended in the data sheet but during debugging the program comes to write to FLASH_ACR to adjust the number of flash wait states and gives Target is not responding.

Thank you.

 

[gbm]

Is PWR module enabled?

[AIBRA.1]

I enabled the clock for Both PWR and Flash interface before Clock Configuration and the problem appears at assigning wait states to Flach_ACR register by showing the target does not respond during the debug session.

[gbm]

By using magic numbers instead of named constants and multiple statements to set a single register you are asking for trouble. Why not:

RCC_>AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN;

Also, FLASH->ACR register contains some important bits set by default. So, to set wait states without turning off the debug interface, use:

FLASH->ACR |= 4u;

[AIBRA.1]

Thank you so much