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I2C SLAVE perform Long clock stretching but 2 units MASTER and SLAVE are configured with the same Frequency

VKats.1
Associate II

Hi,

i am using 2 units of STM32h743II MCU and I am trying to transfer I2C transactions from master to slave based on I2C_TwoBoards_ComPolling examples.

data is received correctly each time but about my i2c slave unit perform Long clock stretching 1 out of every 4/5 transactions.

MASTER configuration:


_legacyfs_online_stmicro_images_0693W00000dDXsrQAG.pnghi2c1.init.timing is overridden with:

I2C_GetTiming(HAL_RCC_GetPCLK2Freq(), BUS_I2C_1000k_FREQUENCY)


_legacyfs_online_stmicro_images_0693W00000dDXshQAG.png 

SLAVE configuration:


_legacyfs_online_stmicro_images_0693W00000dDXt6QAG.pnghi2c2.init.timing is overridden with:

I2C_GetTiming(HAL_RCC_GetPCLK2Freq(), BUS_I2C_1000k_FREQUENCY)


_legacyfs_online_stmicro_images_0693W00000dDXsmQAG.png 

i am using the basic function:

HAL_I2C_Master_Transmit and HAL_I2C_Slave_Receive using STM32Cube MCU Package for STM32H7 series 1.7.0 version but also tried the latest 1.11.0 version drivers.

75% of the i2c transaction seem as expected with out clock stretching:


_legacyfs_online_stmicro_images_0693W00000dDXtLQAW.png 

but 25% are with with long clock stretching:


_legacyfs_online_stmicro_images_0693W00000dDXtQQAW.png 

Please Advise

1 REPLY 1
Bubbles
ST Employee

Hi @VKats.1​,

timing is not really making any difference in stretching, slave is anyway synced using the master clock most of the time. It only stretches, when waiting for SW action, in this case it's for the address ACK. Check the ISR, what is the reaction on ADDR interrupt.

From the reference manual:

In default mode, the I2C slave stretches the SCL clock in the following situations:

• When the ADDR flag is set: the received address matches with one of the enabled

slave addresses. This stretch is released when the ADDR flag is cleared by software setting the ADDRCF bit

BR,

J

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