I need 4 output with pwm feature. All pwm are the same period T of 200 Hz. All pwm have independent dc ( duty cycle ) and independent dt ( dead time ) . Is it possible configure the timer peripheral and the clock to have dead time configurable between 0 t

[stst9187]

Posted on August 31, 2017 at 08:12

I need 4 output with pwm feature.

All pwm are the same period T of 200 Hz.

All pwm have independent dc ( duty cycle ) and independent dt ( dead time ) .

Is it possible configure the timer peripheral and the clock to have dead time configurable between 0 to T/2 ( half period )?

I'm using stm32f052 or stm32f072

thanks

Marco

[Vangelis Fortounas]

Posted on August 31, 2017 at 10:24

Hello !

Dead Time can not be adjusted independently for each channel.

Dead time means at each PWM channel,  are exists two complementary outputs.

Only Timer 1 and 8 have 3 channels with 2 complementary outputs per timer. The other timers don't have this functionality.

Timer 8 is not available in your MCUs

So ..   the answer is  no.

Regards

vf

[waclawek.jan]

Posted on August 31, 2017 at 10:40

I'd go for 4 timers, all set to the same period; TRGO-TRGI linked to each other in daisly-chain fashion, TRGO always taken from an unused channel and determining the phase shift between two successive timers.

JW

[stst9187]

Posted on August 31, 2017 at 11:08

Hi Vangelis 

I thinks that I will use Time1 Timer15 

Timer16 and Timer17, each timer have its dead time, the problem is that I can'0t 

have dead time configurable between 0 to T/2

I thinks

[stst9187]

Posted on August 31, 2017 at 11:11

Hi Jan

sorry but I 'don't' understand, please tell me more thanks ..

[waclawek.jan]

Posted on August 31, 2017 at 14:22

https://community.st.com/0D50X00009XkYAiSAN

[Vangelis Fortounas]

Posted on August 31, 2017 at 15:11

Hi again !

My answer before, based on wrong datasheet resulted from search for stm32f052. Sorry for this

The divison of TimerClock used for producing DWT is maximum  4096 (1024 max from DTG Dead-time generator setup in TIMx_BDTR multiplied by 4 max   from clock division CKD in TIMx_CR1 register)

Here are some examples how to achieve the DWT you desire.

Example 1

To achieve a DWT  time  ~ T/2  Timer clock CLKIN must not exceed 800 KHZ ( eg PSC=0 and ARR 4999  you have freq 200 Hz and period 5 ms) 

In this case  with CKD=2    and   DTG[7:5]=0b111     and   DTG[4:0]= configurable      you can have  5 bit resolution DWT  ( maximum CLkIN / 4096  which means  about half period DWT 5.1 ms)

Example 2

To achieve a DWT  time  ~ T/2  Timer clock CLKIN must not exceed 100 KHZ ( eg PSC=0 and ARR 499  you have period 200 Hz and period 5 ms)

In this case  with CKD=2    and   DTG[7:5]=0b100     and   DTG[5:0]= configurable      you can have  6 bit resolution DWT  ( maximum CLkIN / 256  which means  above half period DWT )

You can clock the timers by using TRGO from other timers ofcourse (master slave configuration).

Its not desirable ofcourse to lower the APB bus toachieve  theese frequencies.. but finaly is an option. 

I Hope to gave you an idea about  all this.

Regards

vf

[stst9187]

Posted on August 31, 2017 at 15:44

Hi VF

What do you mean with '

DWT

'?

Marco

[Vangelis Fortounas]

Posted on August 31, 2017 at 15:52

Hi i mean Dead Time  Typo error

I use frequently the term DWT as 'deadweight' 

Generaly this idea is to lower the freq of a timer to achieve bigger Dead Time.

[Robert Poor]

Posted on August 31, 2017 at 19:46

Frankly, if your PWM period is only 200 Hz and your system doesn't have other time critical processes, you can create software PWMs to do exactly what you need.  You didn't mention what resolution you need, but for 8 bit resolution, your inner loop only needs to run at 51.2Khz, which should be easy on a 48MHz part.

If you do have other time critical processes, you can run them in lock step with the PWM routine.  I used this technique on a lowly PIC processor running at 4MHz to generate 3 PWM channels at 100 Hz, so four channels on a 48MHz part should be a piece of cake...