I have Question about SPI protocol IP's of STM32L475VG DISCOVRY KIT. In polling mode master receive first 2 byte blank. like slave transmit multiple time = "helloworld" master receive like 1st " hellowor" 2nd "ldhellowor" 3nd "ldhellowor"

[NPAGH.1]

Mantion some details

->in this STM32L475VG DISCOVRY KIT Rxfifo and Txfifo of spi is 32-bit

data register is 16-bit

->data register is send on Txfifo and receive from Rxfifo

[TDK]

Sounds like the master and slave are out of sync. You need to ensure the slave is ready to send when CS goes low, and that it's not stuck with stale data. You can re-enable the peripheral to clear the FIFO.

[NPAGH.1]

yes, i was try to complete process of Disable spi and re-enable after every one transaction but not solve.

spi SCL is control by Master so ​,

1) in interrupt mode, working fine because after receiving data in Rxfifo(master​) it start to read.

2) in polling mode, Master start clock and consider Rxfifo(master) is received data based on timing. its possible ?

​so we get blank for first transaction.