About NPAGH.1

NPAGH.1 · 2022-04-14

Mantion some details->in this STM32L475VG DISCOVRY KIT Rxfifo and Txfifo of spi is 32-bit data register is 16-bit ->data register is send on Txfifo and receive from Rxfifo

NPAGH.1 · 2022-04-14

yes, i was try to complete process of Disable spi and re-enable after every one transaction but not solve. spi SCL is control by Master so , 1) in interrupt mode, working fine because after receiving data in Rxfifo(master) it start to read. 2) ...

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I have Question about SPI protocol IP's of STM32L475VG DISCOVRY KIT. In polling mode master receive first 2 byte blank. like slave transmit multiple time = "helloworld" master receive like 1st " hellowor" 2nd "ldhellowor" 3nd "ldhellowor"

Re: I have Question about SPI protocol IP's of STM32L475VG DISCOVRY KIT. In polling mode master receive first 2 byte blank. like slave transmit multiple time = "helloworld" master receive like 1st " hellowor" 2nd "ldhellowor" 3nd "ldhellowor"