I am designing with an STM32H745. I need to use the FMC bus to access my own ASIC. What is the full cycle time on the FMC access if I do back to back single read or single write with multiplexed address/data.

[Sbeny.1]

The access time of the FMC is not the whole equation, I need to include the delays introduced by having to go across domains and buses. Back to back reads or writes would shine more light on this for me. Or possibly a read followed by write so that the accesses do not get posted in a fifo.

Thank you in advance

[waclawek.jan]

Unfortunately, the RM is not very clear in the details and they tend to change between various incarnations of the FMC/FSMC in various STM32 models.

IMO the best thing to do is to experiment, maybe on a Nucleo board with the given chip.

JW

[berendi]

The timing of back-to-back requests would depend on which bus master is issuing them, whatever else is competing for the bus matrix nodes, cache utilization etc.

You can enforce a minimum delay up to 15 fmc_ker_ck cycles by setting the BUSTURN bitfield if this is what you want. This is omitted from the timing diagrams in the datasheet and the reference manual, but somewhat explained in the FSMC register descriptions.

[Sbeny.1]

Thank you both for your responses. I will get the Nucleo and try it.

[waclawek.jan]

> You can enforce a minimum delay up to 15 fmc_ker_ck cycles

> by setting the BUSTURN bitfield

There are exceptions to this (somewhat documented), and then there are exceptions to those exceptions...

https://community.st.com/s/question/0D50X0000C23GN6SQM/f427-fmc-vs-f407-fsmc-different-behaviour-for-backtoback-writes-to-the-same-sram-bank

Enjoy!

JW