About Sbeny.1

Sbeny.1 · 2020-06-24

The access time of the FMC is not the whole equation, I need to include the delays introduced by having to go across domains and buses. Back to back reads or writes would shine more light on this for me. Or possibly a read followed by write so that ...

Sbeny.1 · 2020-06-25

Thank you both for your responses. I will get the Nucleo and try it.

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I am designing with an STM32H745. I need to use the FMC bus to access my own ASIC. What is the full cycle time on the FMC access if I do back to back single read or single write with multiplexed address/data.

Re: I am designing with an STM32H745. I need to use the FMC bus to access my own ASIC. What is the full cycle time on the FMC access if I do back to back single read or single write with multiplexed address/data.