HSE crystal dead

[Nico3]

Hello

I am trying to powerup external 8MHZ crystal on STM32F407VET6 MCU but it is completely dead. I run the LED bliking program using HSI, and it is working sucussfully. Boot 0 and Boot1 pins have been PD with 500 ohm. 

 I also run the same code to use HSE on STM4 Discovery board after removing R68, I see HSE on board is working. 

Below are my caclulation

Frequency = 8 Mhz,

Co = 7 pF ( as per datasheet)

CL= 10 pF ( as per datasheet, used 20pF CL1 and CL2) 

ESR = 100  ohm ( as per data sheet)

After calculation gmcrit comes..

gmcrit = .287 

gm =  5 ( from ST data sheet)

gain margin = 5/.287 = 17    

so gain margin > 5 condition is met. 

I also changed Rext  to 0, 100, 200, 500 , 1000 ohm. HSE is dead. 

PCB design seems ok , and I assume for now no issue with PCB design.

I have gone through AN2867, but not sure what point I am missing.

Kindly suggest where could be the fault.  I eliminate software issue as same code is making HSE work on Discovery board.

[Nico3]

Thanks very much peter, I will get layout corrected. 

Anyway on making sure clock source, I am using same code on STM32F4 Disco board with LED connected to PA1 , it works.

I also see able to see crystal o/p clock on MCO PA8 pin on enabling Master clock output

Configuration used on STM32F4 disco board:

[ONadr.1]

Try putting a crystal from your board into the Disco board. You will verify its functionality.

[Peter BENSCH · Accepted solution]

...and do it step by step:

1. remove the crystal from the DISCOVERY
2. check that the programme is not running on the DISCOVERY, which is correct without the crystal
3. place the other crystal on the DISCOVERY and finally
4. check that the programme (and therefore the crystal) is running

[LCE]

@Peter BENSCH wrote:

• crystal too far away from the STM32
• signal(s) underneath the crystal
• GND around the crystal completely unsuitable:
  • no guard ring around Y1, no separate GND area underneath (see AN2867, section 7.1 and 7.2)
  • No separate and direct GND connection to pin 10 of the STM32

I partly disagree to your comments and the AN:

- The guard ring around the STM-pins on the assembly layer in the AN is so highly unrealistic, or do you still offer packages with a big enough pitch? 

- Split GNDs might be more dangerous than helpful, also depending what's on the next layers

- Too far away, really? Alone the THT size of the crystal is a problem then. And with fully packed designs.

- I only see GND underneath the crystal

I agree that the ground plane should have many more vias - and there's hopefully an internal GND plane directly underneath.

Anyway, I think it should work with this layout. If not, oh my, is that STM32 oscillator that sensitive!?

@Nico3 :

- have you already tried another crystal and other capacitors?

- what's on the next PCB layers?

[Nico3]

Will try other crystal and capacitor as suggested  earlier also. 

It  is two layer PCB . Bottom layer mostly ground.

[LCE]

> two layer PCB

Any reason for that?

Almost any design containing anything switching should be made with 4 layers, with a non-split GND plane adjacent to each signal layer.

Edit: @Peter BENSCH now I see the signal on the bottom layer beneath the crystal. I was hoping for a GND plane underneath...

[Nico3]

Please note Crystal is working now. 

1) I used crystal from DISCO board, still same situation.. not working

2) I used lower CL1 and CL2, still same siutation

3) I changed MCU , Crystal started working. 

I am not sure what went wrong during PCBA with old MCU. It was brand new  and visual inspection was saying good soldering.. ESD protection was also followed...

Anyway finally it is good day today..;)

Thanks again for taking time...

[Nico3]

@LCE 

It may sound crazy, but just to keep lower costs and complexity.. we are keeping only two layer

[LCE]

As long as it works and it passes the EMI CE / FCC tests, 2 layers are fine. :D

[Peter BENSCH]

---

@LCE wrote:

I partly disagree to your comments and the AN:

- The guard ring around the STM-pins on the assembly layer in the AN is so highly unrealistic, or do you still offer packages with a big enough pitch? 

- Split GNDs might be more dangerous than helpful, also depending what's on the next layers

@LCE The guard ring is not meant as a complete enclosure of crystal and oscillator pins, but as a border around the crystals, possibly with an extended edge towards the STM32. The figures of AN2867 mentioned in section 7.2 show this quite well if you look at them carefully.

- Too far away, really? Alone the THT size of the crystal is a problem then. And with fully packed designs.

---

Ok, ok, not necessarily too far away, but the crystal could be moved closer. I've seen a few designs over the last few decades where this has been a problem (but mostly with LSE crystals).

Anyway, I think it should work with this layout. If not, oh my, is that STM32 oscillator that sensitive!?

---

Well, in fact, the HSE oscillator is usually not quite as sensitive as the extremely high-impedance LSE one. However, the different implementation of the HSE oscillator in the various families should not be ignored (gain margin etc). Added to this are the temperature-dependent shifting parameters of the entire oscillator. All in all, it is therefore highly recommended to ensure a super clean layout for the crystals in order to avoid unpleasant surprises such as problems in the field, recalls or necessary relay layouts, not to mention expensive complaints.