Howto Program lowest 32k of Flash when SRAM is mapped there ?

[mike-davies]

Posted on July 31, 2012 at 12:11

Hi,

It's possible to program the Cortex M3 devices so that SRAM is aliased to the addresses starting at 0 and this is useful if it is required to run from RAM whilst supporting a reset vector in SRAM.  However, I do not understand how to program the Flash memory whilst the CPU is in this configuration ?  The PM0062 manual says that half page Flash memory writes are performed by : <snip setup> ''...Directly write half a page with 32 different words to the program memory address space. The words must be written sequentially starting from word 0 and ending with word 31''. But surely if I have mapped SRAM to the lowest 32k in Memory I will be accessing SRAM during this instead of the lowest 32k of Flash, so can anyone tell me how to program the lowest 32k of Flash whilst running from remapped SRAM ? Thanks, Mike

[Tesla DeLorean]

Posted on July 31, 2012 at 13:26

RAM and FLASH always exist at their standard 0x20000000 and 0x08000000 bases, and are typically SHADOWED at ZERO based on the state of BOOT0/1 pins, or registers with latched versions of said.

There is an STM32 quirk when booting from RAM, the reset vector doesn't go where you think, but instead to an explicit RAM address at the end of the vector table for the specific series/model of part. Observe BootRAM vector in GNU/GCC startup, which basically does a ''ldr pc,[4]'' using PC relative encoding. Also I think the quote relates to a page/line within the flash, supposedly you can push out a line of data and then spin and wait. Be aware also that you can run from FLASH while writing/erasing different sections, if you read/execute from FLASH during this time it will STALL the CPU for significant periods, ie it stuffs wait states and can delay from several milli-seconds to several seconds depending on part and operation, and voltage/age.