How to test handling of H7 ECC in SRAM

[aerospace]

Hi all,

When writing tests for handling single and double errors on the STM32H753/43/42/50, there doesn’t appear to be a way to turn off the ECC or access the parity bits to force single or double errors.  Relying on them occurring randomly isn't great and I'd really like to be able to inject known errors at known locations. Flash memory can be tested by judicious overwriting of codewords to manipulate the parity symbols but that technique won’t work on SRAM.

Section 2.5 of AN5342 mentions there may be routines available (which would be great to have) but I can’t find other reference to how this might be done - even if via DAP.

[FBL · Accepted solution]

Hello @aerospace​,

First, RAM ECC cannot be turned off. You can get started with this example. \STM32Cube\Repository\STM32Cube_FW_H7_V1.11.0\Projects\NUCLEO-H745ZI-Q\Examples\RAMECC\RAMECC_ErrorCount

For further details about event monitoring are described in RM0433 Section 3.4: RAMECC_MxSR register. This example can be ported to your STM32H7 MCU.

I hope my answer has helped you. When your question is answered please close this topic by marking as Best the reply that answered you, it will help others find that answer faster. Thanks for your contribution.

[aerospace]

@F.Belaid​ thank you for your reply and the pointer to the example. As I understand it, there is no way to test detection by injecting known errors and need to rely on there being random single and double errors in uninitialised RAM.