How to tell if interrupts are enabled

[DavidNaviaux]

I need to determine if the interrupts are enabled at one point of my code but I have not been able to find any reference for the STM32G474.  It doesn't look like there is a PRIMASK register which is mentions in another post.

I know how do enable and disable the global interrupts: __enable_irq() and __disable_irq(),  but I don't know how to determine if the are enabled.

How can I tell if the global interrupts are enabled?

[AScha.3]

From 

reading the NVIC registers...?

see state of INTs ...:

etc...

[DavidNaviaux]

I am relatively new to Arm Cortex M4 processors.  Some of my functions must be called when the interrupts are enabled or disabled and it must behave differently depending on the interrupt enabled state.  I have been using the following line that I got from another post on this forum about identifying when the interrupts are enabled:

bool bWasEnabled = __get_PRIMASK()&1;

But I have discovered that this does not work for the STM32G474 MCU (although it does not generate a compile error either).  I don't need anything more than this (as long as __disable_irq() and __enable_irq() functions work).

I have tried to find it in the reference manual but without any luck.  It seems that others must know how to do this.

Can anyone give me a line or two of code to identify the state of the global interrupts?

Thank you in advance!

David

[waclawek.jan · Accepted solution]

> I have discovered that this does not work for the STM32G474 MCU

How it "does not work"?

> Can anyone give me a line or two of code to identify the state of the global interrupts?

__get_PRIMASK() is in https://github.com/STMicroelectronics/STM32CubeG4/blob/2d3131ee23ae3e0568c67d367718f37c173af91d/Drivers/CMSIS/Core/Include/cmsis_gcc.h#L449 (provided you use gcc) - __disable_irq() and __enable_irq() is in the same.

Read details of PRIMASK register/bit, CPS(IE/ID) and MRS/MSR instructions in PM0214.

JW

[Tesla DeLorean]

You can unpick the bit vectors in the NVIC to see which sources are monitored, and which are pending.

It's not going to show how many are active or nested. Or which will follow next as it tail-chains out of the current interrupt. Although you might be able to predict.

You can perhaps add something to count up/down in your IRQHandlers, or score board.

Are you using preemption?

Are you blocking in IRQ Handlers or Callbacks?

[Tesla DeLorean]

It might be apparent from stacked content.

Perhaps if it's "protected" on the CM33, use an SVC to query

If it's in an IRQ Handler / Call-Back the interrupts at that same preemption level are effectively disabled. Who runs next is determined as you exit and the tail-chaining determines a winner, or leaves that context.

[DavidNaviaux]

My mistake, I was checking if the bit was set to determine if the interrupts were enabled, but the bit is cleared when the global interrupts are enabled.

Thank you!

David