2022-04-14 02:54 AM
I want my interrupt handler to run in SRAM since some people seem to claim it is a more predictable solution then flash.
I copied my interrupt handler to SRAM using
__attribute__ ((long_call, section (".RamFunc")))
I tested the interrupt by toggling a pin in the interrupt
GPIOC->BSRR = LL_GPIO_PIN_6;
GPIOC->BRR = LL_GPIO_PIN_6;
Since the interrupt is triggered at a frequency of 2MHZ I expect to measure a stable 2 MHZ signal at the output of the scope. There was however a lot of jitter in the result.
I figured placing the interrupt vector in SRAM might solve this problem. The steps I have taken to realize this are:
Updating the linker file
.isr_vectorRAM :
{
. = ALIGN(4);
KEEP(*(.isr_vectorRAM)) /* Startup code */
. = ALIGN(4);
} >RAM
Changing the startup file to place Interrupt vector in SRAM using previous linker code
.section .isr_vectorRAM,"a",%progbits
.type g_pfnVectorsRAM, %object
`.size g_pfnVectorsRAM, .-g_pfnVectorsRAM
g_pfnVectorsRAM:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
Changing VTOR register to vector table address in ram:
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
I verified using build analyzer that the vector table is placed in RAM but the interrupt handler now isn't called anymore since i am not seeing any pulses on the scope.
I have a couple questions about my problem and I was wondering if someone might be able to answer them:
2022-04-14 05:39 AM
2MHz is the problem here, find another way of doing this.
Depending on overall burden/cost of handler, perhaps a few hundred KHz.
For vectors memcpy() to new location with 512 byte alignment, and set SCB->VTOR
2022-04-14 07:51 AM
.isr_vectorRAM :
{
. = ALIGN(4);
ALIGN(4) is not enough for vectors.