2024-03-06 08:38 AM
Hello,
I need to implement delay macro, lasting just a few cycles.
As the delay is so small I would not like to use TIMs o DWT.
On Texas Instruments DSPs, I was used to implement this nanoseconds delays, using NOP() instructions.
Unfortunately, as also written in STM32 Programming Manual this is not a good pattern on Cortex processors.
On a previous post, related to another issue, I was suggested to use Data Memory Barrier (DMB), Data Synchronization Barrier (DSB), and Instruction Synchronization Barrier (ISB) instructions, instead of NOPs.
How can I use this instructions, to implement a few cycles delay macro?
Regards,
Carlo
Solved! Go to Solution.
2024-03-12 02:58 AM
@CTabo.1 wrote:it may be necessary to encapsulate the two consecutive readings instructions between #pragma directives to disable any optimizations.
Possibly, although I'd have thought that the RHS should be qualified as volatile - so might not get optimised?
Maybe alternative to make sts volatile?
2024-03-12 06:50 AM
> However it may be necessary to encapsulate the two consecutive readings instructions between #pragma directives to disable any optimizations.
Registers are marked as volatile. The compiler must read them on every access in your program.
2024-03-12 09:37 AM
Yes, you guys are both right.
The registers are markerd as volatile, so eventual optimizations should not create problems.
Thank you very much,
Carlo