How to enable L1 cache on the stm32f746

[echelon2010]

Posted on September 02, 2015 at 18:32

Hello. I want to enable L1 cache on the stm32f746 controller. In examples from STM32CubeF7 i found that memory protection unit enabled at first and then L1 cache. Is it necessary to enable MPU before L1 cache?

[Tesla DeLorean]

Posted on September 02, 2015 at 19:18

Pretty sure it's not STM32F7 centric, you should probably take the ARM TRM angle on what the core expects and how it functions.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0489c/Chdcghid.html

Review also the CMSIS M7 Core Cache Functions.STM32Cube_FW_F7_V1.0.0\Projects\STM32756G_EVAL\Examples\Cortex\CORTEXM_MPU\Src\main.cSTM32Cube_FW_F7_V1.0.0\Projects\STM32756G_EVAL\Examples\Cortex\CORTEXM_SysTick\Src\main.cCPU_CACHE_Enable() is run with no regard to if the MPU is actually running/enabled.

[Tesla DeLorean]

Posted on September 02, 2015 at 19:19

/**
* @brief CPU L1-Cache enable.
* @param None
* @retval None
*/
static void CPU_CACHE_Enable(void)
{
/* Enable I-Cache */
SCB_EnableICache();
/* Enable D-Cache */
SCB_EnableDCache();
}