Should be decades worth of code examples about how to access NAND memories of this type, including stuff related the linux uboot, etc that can be found online. Plus I'm sure this stuff is documented/described in contemporary data sheets. The memory accesses like a hard drive, the address space is split into a command and data window, and the data sucked out in blocks by doing repeated reads to recover each byte/word. The data blocks can be relatively large at an erase level, but the data itself often goes in a 2048+64 byte type mix of data and ecc/management data.
On the F0 you're going to need to emulate the bus cycles, so driving and sequencing the Read, Write, Address and control signals via GPIO pins associated with each. drive them per timing diagrams in the memory data sheets, and how MCU memory buses are supposed to sequence. For the data bus you're going to have to adjust the input/output states at the GPIO peripheral level, perhaps using Open Drain mode, with pull-ups, and writing 0xFFFF out to get the bus into a read mode, or more actively define the Push-Pull/Input state of the bus based on whether you're emulating a read or write cycle on the simulated bus. I'd suggest mapping the data bus into a linear allocations of pins on a GPIO bank to ease the reading, decoding and mapping into bytes you copy into RAM.
