How to config the FIFO Threshold of OCTOSPI

[rsun.11]

According to my understanding, I can read/write data directly through the "DR" register. Why do I have to set the FIFO Threshold value? How to use the FIFO correctly during the reading and writing procedure?  

And another question is that How to set the "CSHT[5:0]" in "DR1" register? For example How to set the "CSHT[5:0]" if I use "IS25LP064A" Flash?

Thanks

Best Regards

[rsun.11]

No one answer my question?

[Tesla DeLorean · Accepted solution]

Its a forum, there no guarantee anyone will answer your questions, or care, most are more interested in their own problems, and not paid to fix yours.

You don't have to set the FIFO level, but it paces/modulates the IRQ or DMA so they are not continually hammered for every byte, and you can stuff a burst of data in a single transaction.

Read the data sheet for the IS25LP064A, tells you the minimum high time for CE# is 7ns, translate that into clock cycles based on how fast you're clocking the interface so as not to violate this.

[Richard Lowe]

Tesla DeLorean is correct. FIFO level is a trigger level when you need the interrupt be called. If you set it to 1 byte, it will fire an interrupt every byte. Typically, you would configure that level based on the application. If you know you are going to be transferring images, in say a RGB888 format, then you would set the FIFO to something like 3.