2022-12-20 06:36 AM
2022-12-20 07:25 AM
Hello @KJ.4 ,
In a configuration with two or more independent slaves, the master uses GPIO pins to manage the chip select lines for each slave.
The master must select one of the slaves individually by pulling low the GPIO connected to the slave NSS input.
Example: ( see RM0316 section 30.5.3 ) link.
Also as solution, you can work with the 4 SPI instances ( 1,2,3 & 4).
Foued
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2022-12-20 08:02 AM
Missing constrains to narrow down to the right options. ADC spi frequency, bus capacitance load and related bus length, are all the measurements synchronized? How many dma channels for how many spi?
2022-12-20 08:16 AM
What is "CS mode"?
If 8-bit, LSB-first, not-that-high-baudrate is OK, USARTs can be used as SPI masters, too.
JW
2022-12-20 01:00 PM
Thanks for the update Khalsi Foued.
Can I able to connect one MISO and SCLK line to 40 slaves?
Will there be any fanout issues?
I can see input capacitance of Slave is 10pf.
Is this one MISO and SCLK line have enough drive strength to drive 40 slaves?
Please advice on SCLK, MISO & MOSI connections.
2022-12-22 01:13 AM
Hi Khalsi Foued, any update on this question?
2022-12-22 01:40 AM
Can I able to connect one MISO and SCLK line to 40 slaves(AD7719)?
SPI Frequency is 307KHz
2022-12-22 01:41 AM
Chip select mode.
Can I able to connect one MISO and SCLK line to 40 slaves(AD7719)?