How many clock cycles does it take to write a 32 bit value to AXI SRAM?

How many clock cycles should it take to write to AXI SRAM from the M7 core, assuming that the cache is disabled (and disregarding instruction pipelining)?

The reference manual says:

"The system AHB SRAM can be accessed as bytes, half-words (16-bit units) or words (32-bit 

units), while the system AXI SRAM can be accessed as bytes, half-words, words or double-

words (64-bit units). These memories can be addressed at maximum system clock 

frequency without wait state." [emphasis mine]

I assume that accessing the AXI SRAM isn't always zero wait state because:

• In that case, the manual would have said so
• It'd obviate the need for the DTCM RAM
• My testing indicates that writes and reads (i.e., STR and LDR) take 8 clock cycles

I'd love to confirm the results of my testing with hard numbers from the reference manual or an application note, or other credible source.

Thanks,

Richard