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How long does the NRST pin has to be held low to trigger a reset (STM32F103RC) ?

Associate II

In my design, I have two MCUs, the STM32F103RCT6 and an ESP32. At some point, the ESP32 will perform a firmware update of the STM32. So it will need to reset it through the NRST pin, controlled through a GPIO. I have checked rapidly the datasheet, the reference manual, the application note 2606 and 3155, and the only reference to timing is the following (reference manual) :

"The system reset signal provided to the device is output on the NRST pin. The pulse

generator guarantees a minimum reset pulse duration of 20 μs for each reset source

(external or internal reset). In case of an external reset, the reset pulse is generated while

the NRST pin is asserted low."

But that doesn't really say how long should the NRST pin asserted low, is it 20µs too or something else ? Note that I already have something working with a NRST pin held low during approximately 80µs, but it would be nice to have this information.

Uwe Bonnes

Normally you have about 100 nF to ground and a 50 kOhm internal pullup as NRST wiring. As soon as you hit the lower threshold at the reset pin at 0.3 Vddio and you immediate release NRSR you can calculate yourself wehn the NRST input high level at 0.7 Vddio is reached...

Thanks, but I know how to calculate a time constant in a RC circuit. The question that I'm asking is how much time does it need to stay low, not how much time I will need to drive the pin low.

You've got it attached to another microcontroller, couldn't you just parametize it yourself? The documentation is basically saying it needs 20 us to reset properly internally., and have tried to fool proof it.

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Associate III

I just found this post and have the same question. I'm looking for data on how long I should assert NRST and how long the boot pin needs to be held before it is sampled. This is basic information that seems to be missing from the datasheets.