how i can connect External SRAM to STM32F103Zxxx chip

[eittinfo]

Posted on April 08, 2014 at 00:49

Hi

I want to connect external 512KByte SRAM to my stm32f103zxx.please help me to connect external sram memory to chip.i have a ''HM628512BLFP-5'' 512KByte CMOS Static RAM chip.datasheet:please help me.thanks #crap-by-design #sram

[Tesla DeLorean]

Posted on April 08, 2014 at 01:13

If the part you are using has an external bus (FSMC), I would suggest review schematics for available boards like the STM3210E-EVAL, or other third-party boards, to become familiar with how this is achieved.

[eittinfo]

Posted on April 08, 2014 at 09:14

thanks.

in STM3210E-EVAL schematic sram chip have two signal FSMC_NBL0 and FSMC_NBL1.my sram chip have not those signal. how i can connect this chip in my board? what different FSMC_NE1 with FSMC_NE2 or FSMC_NE3 signals? please show me how i can connect my sram chip. thanks ====================== From: clive1Posted: Tuesday, April 08, 2014 1:13 AMSubject: how i can connect External SRAM to STM32F103Zxxx chip

If the part you are using has an external bus (FSMC), I would suggest review schematics for available boards like the STM3210E-EVAL, or other third-party boards, to become familiar with how this is achieved.

[Tesla DeLorean]

Posted on April 08, 2014 at 09:34

You'd likely need two of the parts, the FSMC wants to work with 16-bit wide memories, the NBL would control which chip, or both were being accessed.

Only the NAND/PCCARD connectivity supports 8-bit wide memory. Pick a SRAM part that meets the requirements. Review the FSMC chapter in the RM0008 Reference Manual.

[waclawek.jan]

Posted on April 09, 2014 at 12:09

> Only the NAND/PCCARD connectivity supports 8-bit wide memory.

I don't think so - what would then be the purpose of FSMC_BCR.MWID bits? JW

[Tesla DeLorean]

Posted on April 09, 2014 at 13:29

I agree that they should be, but the documentation is not throughly supportive of there use, there are a number of awkward tables and phrases in RM0008

''NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).'' ''PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).'' I would still look for a reference design demonstrating it, and check if the further degradation of speed solved more problems than it created.

[waclawek.jan]

Posted on April 09, 2014 at 13:51

Yes we all know that the documentation is crap.

I would assume the cryptic ''addressed in 16-bit words'' remark came simply from the incompetency of the writer (there's more such - in the first lines of 21.5 there's reference to 32-bit async SRAM/ROM, which is again clearly nonsense). 26 adress lines clearly refers to 8-bit data bus, so does Table 101. Whether it makes sense to use an 8-bit SRAM, is to be left to the decision of the designer. There are designs where speed does not matter but pin count and/or PCB area does. JW

[Tesla DeLorean]

Posted on April 09, 2014 at 14:01

It appears to me from the topic (tables, examples, timings)  coverage, that the use of 8-bit memory was purposefully avoided.