2020-06-03 12:01 AM
2020-06-03 04:52 AM
CAN memory is organized as a queue so it is not directly addressable. There are two receive FIFO queues, one for high priority messages and one for low priority. Filtering masks determine which FIFO to use when a message is passed through the filter. This is in line with the CAN bus design where the message identifier also determines priority on the bus when collisions occur, where a high priority message with a lower ID number takes precedence by being received into the high priority RX FIFO. The application should always empty the high priority FIFO before handling data from the low priority FIFO.
There are three transmit mailboxes (a single message queue). These are emptied by the CAN peripheral as space becomes available on the CAN bus. Data is written to the first available mailbox from the application.
Jack Peacock
2020-06-03 04:54 AM
Hey thank you for replying, what i want to know actually is that is it DMA or what exactly?
2020-06-03 07:09 AM
It is not DMA. Data transfers are to/from a register location in the CAN peripheral. You cannot directly access the CAN buffer memory. You must read a word at a time from the data register. After each read the next word is loaded from the internal FIFO.
Jack Peacock
2020-06-03 07:34 AM
The STM32 has a CAN controller, it just manages traffic on/off the wired interface. The Reference Manual does have a reasonable outline of the controller, and there are probably better Web resources describing the wire level protocol and functionality.
CAN is used to send small packets of information between nodes on the network, for example command to lock or unlock a door, open a window, report engine RPM, etc.
On the CPU side you need to manage the dispatch and reception of packets from the controller.
The interactions are better managed in an interrupt handler as this will improve responsiveness and bus utilization.
Find someone locally familiar with CAN usage and use cases.