High speed work with GPIOs - help needed

[morpeh89]

Posted on September 30, 2010 at 09:03

High speed work with GPIOs - help needed

[John F.]

Posted on May 17, 2011 at 14:09

The choice of 2, 10 or 50 MHz sets the rate at which the driver hardware output will transition from high to low or low to high (once the instruction to do so has been received). Slower speeds use less power and create less electrical noise. It doesn't affect anything else.

It sounds like you need to add some external hardware latch or logic (whose operation may be controlled by the microcontroller if you wish).

[epassoni950]

Posted on May 17, 2011 at 14:09

Hello,

Maximum frequency for output GPIO is 18 MHz. With a 103 running at 72 Mhz, you need one STR instruction to write to BSRR to put pin at high and another STR instruction to write BRR to put pin at low. Each instruction is 2 cycles, so there are 4 cycles for the 2 instructions : 72 / 4 = 18 MHz. You can have this if your processor do nothing else, and you must repeat the 2 instructions more times in Flash. If you have a branch, time between low to high or high to increases. You must note also that use write to BRR and BSRR is faster than using bit-banding. For bit-banding, you one STR instruction in your code but core execute a read to register ODR, a bit modification and then a write to ODR. I think that a STM32 is not the good choice for your application with signal at 30 ns. Best regards Eric

[Tesla DeLorean]

Posted on May 17, 2011 at 14:09

I think that a STM32 is not the good choice for your application with signal at 30 ns.

Yeah, in the real world we do that with hardware, it's not a ''software'' task.

[lowpowermcu]

Posted on May 17, 2011 at 14:09

Hi clive1 & John F.

What about using event out cortex (event out) ? Perhaps It can be useful for Otachkin. Thanks in advance for your clarification. regards, MCU Lüfter

[Tesla DeLorean]

Posted on May 17, 2011 at 14:09

>>What about using event out cortex (event out) ?

What is this? Which pin/function of the STM32 are we talking about? 30ns, that's about 33 MHz. I can't see how you are going to be able to get the signal on chip, propagate it from one GPIO to another GPIO, and get it off chip in the window available. Let alone interrupt and react to it (

sychronization

+ latency), the out-of-sequence flash read is going to require at least 30-35ns.

[sros]

Posted on May 17, 2011 at 14:09

How about using SPI and DMA for reading (and maybe wrinting) data?

I guess you could reach sampling rate up to 36 MHz. For example I am using SPI with DMA for sampling signals into memory. While SPI and DMA are filling the the buffer timer interrupts are used to analyse the data (following the DMA in discrete steps).