High accurate sine wave using STM32H7

[GHARI.1]

Hello,

Is it possible to generate high accuracy in terms of the frequency sine wave using STM32?

My goal is to generate a sine wave using STM32 whose frequency varies from 5KHz to 20KHz insteps of 0.1Hz with a delay of 1 sec is it possible to use STM32?

[Uwe Bonnes]

Define high accurate. The builtin DAC has 1 MHz, so you can do 50 samples of a full sine wave for the 20 kHz output.

[GHARI.1]

The generated sine wave frequency should be +/-0.1Hz variation from dailed frequency

[Michal Dudka]

H7 can run DAC at 18Msps.

[Michal Dudka]

Will be complicated. Depends on sinewave shape quality. For example if you select 64 points in one sine period, then you will need 20k*64=1.28Msps. That sampling frequency is derived from chip clock. Suppose that chip clock is 550MHz. Then you need prescale clock by value 429.6875. You have to choose use prescaling 429 which leads to sine frequency 550MHz/429/64 = 20.032kHz or 430 which lead to 550MHz/430/64 = 19.985kHz. Frequency step is 47Hz. That is 470x worse then you need. You can change number of samples in sine which brings you abour 64x better frequency resolution but that is not enought. Next you can adapt PLL to change clock frequency which possibly can bring you another frequency resolution and takes you near desired 0.1Hz step. It is "on the edge" and may be you will need much more pure sinewave then from 64 steps. Look for external DDS chip, it do the job simple.

[GHARI.1]

Can we implement DDS logic on STM32H7​

[TDK]

It's definitely doable, but getting 0.1 Hz variation is difficult.

You can drive the DAC using a timer and vary the period of that timer using a DMA transfer to ARR. This will let you get better precision than a fixed period.

At a timer speed of 168 MHz and a output frequency of 20000 Hz, you need 8400 ticks.

At a timer speed of 168 MHz and a output frequency of 20000.1 Hz, you need 8399.96 ticks.

So you need a resolution of 0.04 ticks, which you can get by adjusting the period of the timer by 1 every 25 cycles which you can do with an ARR array length of 25.

So very much doable, but will take some expertise.