2020-05-31 02:45 AM
HAL_GPIO_WritePin(dac_cs_GPIO_Port, dac_cs_Pin, GPIO_PIN_RESET);////Select SPI
DAC_Data = (DAC_Data&0x0FFF)<<2 ;
uint8_t DAC_Data1= (uint8_t)((DAC_Data>>8)&0x00FF);
uint8_t DAC_Data2= (uint8_t)(DAC_Data&0x00FF);
HAL_SPI_Transmit(&hspi1,DAC_Data1,10,100);
HAL_SPI_Transmit(&hspi1,DAC_Data2,10,100);
HAL_GPIO_WritePin(dac_cs_GPIO_Port, dac_cs_Pin, GPIO_PIN_SET);//Deselect SPI
int BitNo;
dis_intrpt ; //Stop interrupts
//***************** bits banging*****************
if(RegAdd&(0x01<<5)) {MOSI_H;}// mosi_h means mosi=1
else MOSI_L;//Assert 6th address bit to MOSI line// mosi_l means mosi=0
HAL_GPIO_WritePin(GPIOA, spi_cs_Pin, GPIO_PIN_SET); //Select SPI
//EA=0; //Stop interrupts
for(BitNo=5;BitNo>0;BitNo--)
{
delay_1u(10);
SCLK_H;delay_1u(10); //Raise clock and wait H width
SCLK_L; //Lower clock and
if(RegAdd&(0x01<<(BitNo-1))) {MOSI_H;}
else MOSI_L;//Assert Reg add bit to MOSI line
}
2020-05-31 05:56 AM
Set the SCLK and MOSI pins as GPIO output before bit-banging in the GPIO MODER register. Set them back to alternate mode when using the SPI controller.
Check the datasheet of the bit-banged slave. Does it really require CS high during transmit?
BTW the SPI controller should support 6 bit transfers, check the description of SPI control register 2 (SPIx_CR2) in the reference manual.