Help with STM32U0 RTC not running wanted

[Uwe Bonnes]

Hello,

probably I miss something, but  I have searched long enough so things start to get unclear.
I have set up RTC on STM32U0, so I expect is to be running. But ist does not free running:

<(gdb) mon s
Target voltage: 3.24V
Available Targets:
No. Att Driver
1 STM32U07 M0+
(gdb) att 1
Attaching to program: /samsung/home/bon/devel/en_apps/caltime/stm32u083c-dk/caltime.elf, Remote target
0x08004a00 in Stm32RtcV2PollSync ()
at /samsung/home/bon/devel/en_apps/ethernut/nut/arch/cm3/dev/stm/stm32_rtc_v2.c:110
110 while ((RTC->ICSR & RTC_ICSR_RSF) != RTC_ICSR_RSF);
(gdb) p /x *RTC
$1 = {TR = 0x164928, DR = 0x249024, SSR = 0xff, ICSR = 0x17, PRER = 0x7f00ff, WUTR = 0xffff,
CR = 0x3000, RESERVED0 = {0x0, 0x0}, WPR = 0x0, CALR = 0x0, SHIFTR = 0x0, TSTR = 0x0,
TSDR = 0x0, TSSSR = 0x0, RESERVED1 = 0x0, ALRMAR = 0x0, ALRMASSR = 0x0, ALRMBR = 0x0,
ALRMBSSR = 0x0, SR = 0x0, MISR = 0x0, RESERVED2 = 0x0, SCR = 0x0, RESERVED3 = {0x0, 0x0, 0x0,
0x0}, ALRABINR = 0x0, ALRBBINR = 0x0}
(gdb) p /x *RTC
$2 = {TR = 0x164928, DR = 0x249024, SSR = 0xff, ICSR = 0x17, PRER = 0x7f00ff, WUTR = 0xffff,
CR = 0x3000, RESERVED0 = {0x0, 0x0}, WPR = 0x0, CALR = 0x0, SHIFTR = 0x0, TSTR = 0x0,
TSDR = 0x0, TSSSR = 0x0, RESERVED1 = 0x0, ALRMAR = 0x0, ALRMASSR = 0x0, ALRMBR = 0x0,
ALRMBSSR = 0x0, SR = 0x0, MISR = 0x0, RESERVED2 = 0x0, SCR = 0x0, RESERVED3 = {0x0, 0x0, 0x0,
0x0}, ALRABINR = 0x0, ALRBBINR = 0x0}
(gdb) p /x RCC->BDCR
$3 = 0x8103
(gdb) p /x RCC->APBSMENR1 & RCC_APBSMENR1_RTCAPBSMEN
$4 = 0x400
(gdb) p /x RCC->APBENR1 & RCC_APBENR1_RTCAPBEN
$5 = 0x400
(gdb) c
Continuing.
^C
Program received signal SIGINT, Interrupt.
Stm32RtcGetClock (rtc=0x2000040c <rtcStm32>, tm=0x20000c1c)
at /samsung/home/bon/devel/en_apps/ethernut/nut/arch/cm3/dev/stm/stm32_rtc_v2.c:356
356 Stm32RtcV2PollSync();
(gdb) p /x RCC->APBENR1 & RCC_APBENR1_RTCAPBEN
$6 = 0x400
(gdb) p /x *RTC
$7 = {TR = 0x164928, DR = 0x249024, SSR = 0xff, ICSR = 0x17, PRER = 0x7f00ff, WUTR = 0xffff,
CR = 0x3000, RESERVED0 = {0x0, 0x0}, WPR = 0x0, CALR = 0x0, SHIFTR = 0x0, TSTR = 0x0,
TSDR = 0x0, TSSSR = 0x0, RESERVED1 = 0x0, ALRMAR = 0x0, ALRMASSR = 0x0, ALRMBR = 0x0,
ALRMBSSR = 0x0, SR = 0x0, MISR = 0x0, RESERVED2 = 0x0, SCR = 0x0, RESERVED3 = {0x0, 0x0, 0x0,
0x0}, ALRABINR = 0x0, ALRBBINR = 0x0}>

This is on a stm32u583c-dk board. LSE is select and running. ABH clock  enabled in normal and in sleep mode etc. RSF never gets set again and debugger also reads no new RTC values.

Any ideas? Thanks

[waclawek.jan]

All registers look good.

> LSE is select and running.

How do you know? Can you try check it through LSCO/MCO, or through the feed to TIM16?

How is VBAT connected?

JW

[Uwe Bonnes]

RCC_BDCR_LSERDY is set, so LSE is stable. Connections are as of stm32u083c-dk,  VBAT to VDDMCU.

[Uwe Bonnes]

RTC does also not increment  when switching to LSI as RTC source with RCC_CSR_LSIRDY set.

[Uwe Bonnes]

More observations: With RTC_CR_BYPSHAD set, RTC does update.

[waclawek.jan]

Hi Uwe,

> RCC_BDCR_LSERDY is set, so LSE is stable.

Not necessarily. This may be different with 'U0, but on older STM32, LSERDY/HSERDY don't indicate the *current* state of oscillator; rather, they indicate that since startup there has been some number of oscillation detected. In other words, if the oscillator starts up properly, and then later dies for whatever reason, LSERDY may remain high.

But even then, the two informations you've posted appear to indicate that it's the syncrhonization mechanism (BYPSHAD=0) which does not work. There may be requirements on APB-to-RTC clock frequency ratios, can you please check them?

JW

[Uwe Bonnes]

It is the same  code, beside some #defined forAPB Clock enable and EXT RTC line settints, that  runs on f0-f7, l0-l4, g0/4 and U5. I can get the code to run by setting BYPSHAD=1 and not waiting for RSF before register read in the U0 case. U0 runs at 56 MHz processor speed from PLL and USART2 works as expected, so clock ration APB to RTCCLK should be no issue.
I suspect some "easter egg" register bit needed to be set as BDCR_LSESYSEN needs to be set to run LCD on U0 with LSE

[waclawek.jan]

Try to reduce the program or write a new, minimal, exhibiting the problem, and post.

JW