Hard Fault in FLASH_ReadAccess64Cmd(ENABLE)

[mailmail9117]

Posted on February 28, 2013 at 22:55

I am getting a Hard Fault in FLASH_ReadAccess64Cmd(ENABLE). The line is

FLASH->ACR |= FLASH_ACR_ACC64; When I cold boot, it seems to work fine, but if I reset in the debugger it can't seem to get by this function. The code that runs AFTER this messes with the clock and flash settings a lot, so the clock/pwr/flash may be in an unknown state prior to the reset. The sequence of setup function calls is RCC_DeInit(); RCC->CR |= RCC_CR_HSION; while ((RCC->CR & RCC_CR_HSIRDY)==0); RCC->CFGR &= (uint32_t)0x88FFC00C; RCC->CR &= (uint32_t)0xEEFEFFFE; RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CFGR &= (uint32_t)0xFF02FFFF; RCC->CIR = 0x00000000; FLASH_ReadAccess64Cmd(ENABLE); Nothing runs before this. Power (3.3V) is stable. Ideas? #hardfault-flash-access

[Tesla DeLorean]

Posted on February 28, 2013 at 23:32

Looks to be STM32L1xx code

Doesn't this turn HSI OFF?! RCC->CR &= (uint32_t)0xEEFEFFFE; The code expects MSI to be running. System restarts with MSI 2 MHz and 0 Wait States. Using DeInit on a already running system is not usually a good plan, neither is switching to clocks not running, etc. Make sure the debugger's reset is a real reset, not some lame reload of the SP/PC from the vector table. If it isn't doing a real reset, then your clock set up code needs to be a lot more defensive, and establish what clocks, wait states, etc are actually in use, and get the CPU into a safe state from which to migrate to other settings. Is this code in SystemInit() or some place else? This is code to switch to HSI from one of the examples

void SetHSICLK(void)
{
/* Enable HSI Clock */
RCC_HSICmd(ENABLE);
/*!< Wait till HSI is ready */
while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
/* Enable 64-bit access */
FLASH_ReadAccess64Cmd(ENABLE);
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(ENABLE);
/* Flash 1 wait state */
FLASH_SetLatency(FLASH_Latency_1);
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
while (RCC_GetSYSCLKSource() != 0x04);
RCC_HCLKConfig(RCC_SYSCLK_Div1); 
/* PCLK2 = HCLK */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* PCLK1 = HCLK */
RCC_PCLK1Config(RCC_HCLK_Div1); 
}