H743zit6, Abnormal data reception using SPIDMA mode?

[AASD.1]

All data received in normal mode is 0, but some correct data can be received in debug mode？

cubemx configurations are as follows：

• Part of the code is as follows:

uint8_t pData[128] = {0x00};
HAL_SPI_Receive_DMA(&hspi1,pData,128);
while(HAL_SPI_GetState(&hspi1) != HAL_SPI_STATE_READY);
while(CDC_Transmit_FS(pData,128) != USBD_OK);
while(CDC_Transmit_FS(TestData,1) != USBD_OK); //0xff

• In normal mode, SPIDMA receives 128 bytes of data and returns it to the host computer using a usb virtual serial port (the host computer displays a column of 20 bytes). At this time, no matter how many times it is received, it is all zero, but the waveform is correct.
• Debug mode receives partially correct data (data format is 128 bytes of data consisting of two identical 64 bytes). The first 64 bytes received are correct, the last 64 bytes are not sure where the error occurred), and the last 0xff is used to test whether the USB is normal. The following figure (where DOUT is the slave output waveform) :

• In normal mode, it's all zero.

• In debug mode, some correct data can be received.

The monitor variable is indeed the same as displayed after receiving by the upper computer, again proving that the upper computer has no problem with USB transmission.

Questions:

1. Why is there a difference between debug mode and normal mode?
2. How can SPI+DMA fully receive 128 bytes?

​ Thanks for your suggestions and reply.

There is original address:https://shequ.stmicroelectronics.cn/thread-640472-1-1.html

[AScha.3]

I see no cache management, so try: switch off D-cache , then try again.

[AASD.1]

How to switch off D-cache? I use this function

//  /* Enable I-Cache---------------------------------------------------------*/
  SCB_EnableICache();
 
//  /* Enable D-Cache---------------------------------------------------------*/
  SCB_EnableDCache();

in main.c.Is it?

[AASD.1]

Thanks you.it could recevie data normally after I remove SCB_EnableDCache().

[AASD.1]

Could I ask why it has to do with D-cache?

[AScha.3 · Accepted solution]

yepp. 🙂

very basic standard problem: dma and cpu are both "master" on internal bus+memory ;

when D-cache buffers data, it is buffering memory wherever it could "help" the cpu to get without wait cycles the variables or data.

now dma writing some data in memory - but cache controller can not know about this action. So you get possibility memory has new data, but cpu still see "old" data in cache (for same adress).

simple solution: switch off D-cache.

perfect: use MMU or cache management ("invalidate cache" etc. ) to let the cache controller know, what memory areas are or maybe invalid.