H7 SPI Issue: 4us delay between enabling SPI transmission to starting the clock. How can I reduce this time?

[BamBam]

I use a STM32H723VGT6 as a master in a critical SPI communication with another microcontroller (critical because this mcu is very strict in the SPI timing, especially the time between CS and the start of CLK, and I cannot operate on the firmware of this MCU), this is my configuration:

HW setup:

SysClock 320MHz

SPI3 Clock 40MHz(PLL3P)

SPI setup:

 hspi3.Instance = SPI3;

 hspi3.Init.Mode = SPI_MODE_MASTER;

 hspi3.Init.Direction = SPI_DIRECTION_2LINES;

 hspi3.Init.DataSize = SPI_DATASIZE_8BIT;

 hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;

 hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;

 hspi3.Init.NSS = SPI_NSS_SOFT;

 hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;

 hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;

 hspi3.Init.TIMode = SPI_TIMODE_DISABLE;

 hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

 hspi3.Init.CRCPolynomial = 0x0;

 hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;

 hspi3.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;

 hspi3.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;

 hspi3.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

 hspi3.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

 hspi3.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;

 hspi3.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;

 hspi3.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;

 hspi3.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;

 hspi3.Init.IOSwap = SPI_IO_SWAP_DISABLE;

 if (HAL_SPI_Init(&hspi3) != HAL_OK)

 {

  Error_Handler();

 }

SPI send function prototype:

clear_ext_cs0_pin();

&hspi3->Instance->CR1 |= SPI_CR1_SPE;

&hspi3->Instance->CR1 |= SPI_CR1_CSTART;

&hspi3->Instance->TXDR = data;

This is the time used by SPI to start the transmission:

[TDK]

Use more direct register access, ensure compiler optimizations are on. Rewrite clear_ext_cs0_pin as a direct register access or create a macro which does so. Not sure CSTART is what you want here.

Don't set CS low until just prior to shipping data.

SPI3->CR1 |= SPI_CR1_SPE;
GPIOx->BSRR = ...;
SPI3->TXDR = data;

[BamBam]

Hi TDK and thanks for your fast replay

What do you mean with: "Not sure CSTART is what you want her"?

From Reference manual, "Procedure for enabling SPI" 55.4.10:

'The master at full duplex (or in any transmit-only mode) starts to communicate when the SPI

is enabled, the CSTART bit is set and the TxFIFO is not empty, or with the next write to

TxFIFO.'

Also HAL_SPI_TransmitReceive(..) function set it to start transfer in master mode:

  if (hspi->Init.Mode == SPI_MODE_MASTER)
  {
    /* Master transfer start */
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
  }

Compiler optimization is set to Ofast, I also have implemented your tips for CS management with direct access to GPIO registers, but unfortunately don't help to solve this issue.

[Pavel A.]

SPI master of STM32H7 can operate in two modes: "packet mode" where the transaction is started by SPI_CR1_CSTART, and "just clock it out" started by write to the TXDR. You may want to use the latter mode, it is simpler.

Also, look into using hardware-driven CS output (NSS not 'soft'). This will automatically synchronize driving CS and starting the clock.

[BamBam]

Hi Pavel, thanks for your help,

Could you give me some references about this SPI modes? Maybe I missed somethings but i can't find anything in Reference manual

[waclawek.jan]

> Could you give me some references about this SPI modes? Maybe I missed somethings but i can't find anything in Reference manual

And have you read it thoroughly? Pavel references mainly to description of TSIZE/TSER/CSTART mechanism - read description of those fields in the registers subchapter of SPI chapter, and also the Sequence handling subchapter.

However, the 'H7 SPI is an overcomplicated beast and even if the SPI chapter is rather lengthy, I doubt timing details are described in RM in sufficient detail. I personally would start with setting SPE and CSTART well before the need for communication, in the initialization stage, and then only write to DR, as in the "normal" STM32 SPIs. Of course, for any real work, Cube/HAL is just an obstacle.

I don't use the 'H7.

JW