Guarantee write to timer preload-enabled PSC and ARR registers get applied together

[Pete Dietl]

Imagine that:

1. I am using a timer in PWM mode.
2. The timer is running.
3. Interrupts are disabled.
4. The timer is in downcounting mode.
5. Pre-load is enabled for the PSC, ARR, and CCR registers.
6. I need to update the PSC and (ARR or CCR (or both)).

Imaging I am using the following code:

irq_disable();
TIMx->PSC = foo;
TIMx->ARR = bar;
irq_enable();

Is it possible for the following to occur:

1. Line 2 executes and the PSC shadow register is updated.
2. The timer CNT register reaches 0 and an UEV is generated.
3. The timer's real PSC register gets the value from the shadow register.
4. The timer continues doing its thing.
5. Line 3 executes.

And now my intended simultaneous update of PSC and ARR are split -- that is, the ARR will only be really updated to bar on the next timer update event.

Can this situation occur? Is there any way to protect against this?

The only solution I can think of is waiting to update any of PSC, ARR, and CCR and writing those registers only in the next UEV interrupt handler, where I know that I have some time before the next update event occurs.

[waclawek.jan]

Another way is to use Update-initiated DMA through the DMAR/DCR mechanism.

But perhaps the easiest/laziest :) method is to temporarily disable the "natural" updates using TIMx_CR1.UDIS bit.

JW