GPIO pins 8 bit bidirectional data configuration?

[siddj]

Posted on February 16, 2009 at 12:10

GPIO pins 8 bit bidirectional data configuration?

[siddj]

Posted on May 17, 2011 at 13:02

I need to configure 8 GPIO pins for 8 bit bidirectional data to my XILINX CPLD.

What would be the best way to configure my GPIO for that purpose? I am using STM32F103-VET6. Thanks for your help!

[16-32micros]

Posted on May 17, 2011 at 13:02

Hi,

You can use the I/O configured as Open-Drain , in that case you will get : � Open Drain Mode enabled : A “0� in the Output register activates the N-MOS while a “1� in the Output register leaves the port in Hi-Z. � The Schmitt Trigger Input is activated. � The weak pull-up and pull-down resistors are disabled. � The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle � A read access to the Input Data Register gets the I/O state in open drain mode Cheers, STOne-32.

[st3]

Posted on May 17, 2011 at 13:02

Quote:

You can use the I/O configured as Open-Drain

Sounds like the good ol' 8051 ''quasi-bidirectional'' approach... 8-)

[siddj]

Posted on May 17, 2011 at 13:02

So is that AF open drain or Output open drain configuration?

thanks ...

[16-32micros]

Posted on May 17, 2011 at 13:02

Output open drain

[sofiene]

Posted on May 17, 2011 at 13:02

You can either:

- Configure your 8 pins as output open-drain and use 8 pull up rtesistors in ech pin. In this cas you can read or write over the 8 pins without reconfiguring the GPIOs. - Or, configure your 8 GPIOs each time (as input or output) you read or write from the CPLD. So you have to synchronize with the XILINX CPLD the data direction to avoid short-circuits by using other GPIO to indicate read or write transaction. B.R. M3allem

[jj]

Posted on May 17, 2011 at 13:02

I've a concern - ''Output Open Drain'' will work if ALL devices on that particular signal bus ''also'' operate, ''Output Open Drain.'' Now the CPLD may not operate in ''Output Open Drain'' - if it operates in a ''sourcing current'' mode (ie. push-pull) you may cause excessive current flow when the CPLD outputs a logic ''high.''

Thinking further - there must be a mechanism w/in STM32 so that an ''Output Open Drain'' set to ''low'' does NOT remain active when the STM32 is ''reading'' from an external device. (in this case - the external device could never assert a ''high.'' Final point - when high speed is a goal - would not ''Output Open Drain'' be a less than optimal choice?