GPIO configuration for i2c and spi

hate_pod · ‎2011-11-21

Posted on November 21, 2011 at 22:45

In principle, i2c and spi interfaces need open drain connections with (data) lines connected to pull-up resistors.

However, in all the sample codes of the STM32 (examples in the peripheral library), the GPIOs for these peripherals are configured as push-pull with (internal) pull-down resistors.

What could be the reason for this choice? Could it be that internal pull-up resistors of STM32 are too big (approximately 40K) to support fast communication?

In case I don't want to use external pull-up resistors for spi and i2c lines, should I prefer using open-drain with pull-up resistor configuration or push-pull with pull-down resistor configuration

(as in the examples)

for the GPIOs?

Tesla DeLorean · ‎2011-11-21

Posted on November 21, 2011 at 23:30

In principle, i2c and spi interfaces need open drain connections with (data) lines connected to pull-up resistors.

SPI virtually never uses Open-Drain. It's designed to be a high speed interface. There are half-duplex modes, by those are atypical.

I2C is designed to exclusively use Open-Drain. It's designed to run with multiple slave devices, across multiple boards, and relatively slowly 400 KHz. You're going to want to use external pull-up resistors, as the poly-silicon ones on the chip are pretty weak, a stronger 4K7 would be more appropriate.

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ColdWeather · ‎2011-11-22

Posted on November 22, 2011 at 10:54

Hello!

Regarding SPI I would add to the answer from clive1 the following.

SPI SCK, MOSI (and NSS as software driven) to be PushPull to provide the high speed signals (tens of MHz). No internal pull-ups/-downs are neccessary in this case: they would be useless. Another question is, though, how the SPI peripherals would act upon the start up (power on) of the system while the CPU is not running yet. Upon start up all CPU pins are inputs and thus floating. The logical states are undefined. The SPI peripherals may interpret these states in a wrong way. To prevent this, external pull-ups/-downs maybe usefull. Mostly SCK and NSS are important. Usually a rising edge on SCK would latch the data into the peripheral, while low NSS selects it. Thus, an external pull-down resistor at SCK and a pull-up at NSS, both about 10K, would help to keep the lines in the definite states until the CPU has booted.