Getting SDMMC to work with DMA2 Channel 4

[Simone Agha]

Posted on May 04, 2018 at 17:06

I'm using a STM32L461VGTx and am trying to implement the SDMMC peripheral to read and write to a SD card using DMA. I've adapted CubeMX FatFs_uSD_DMA_Standalone example to my project which uses a simpler, custom file system. The problem I'm seeing is this: I can get DMA2 Channel 5 to work but not DMA2 Channel 4. I've set up both DMA channels using CubeMX with the following settings:

• Priority: Low
• DMA Request Settings: Mode: Normal
• DMA Request Settings: Increment Address: Memory checked
• Data Width: Peripheral: Word
• Data Width: Memory: Word

I've tried swapping the DMA channels assigned to SDMMC Rx and Tx, and that doesn't help: it's always DMA2 Channel 4 that does not work regardless of whether it is handling Rx or Tx.

Specifically, I am calling HAL_SD_ReadBlocks_DMA or HAL_SD_WriteBlocks_DMA and waiting in a while loop for the operation to complete. The conditions I'm waiting for are:

1. HAL_SD_GetState != HAL_SD_STATE_BUSY
2. HAL_SD_GetCardState == HAL_SD_CARD_TRANSFER
3. The DMA complete flag is set
4.  If 1-3 do not happen, then I timeout after 30000 ms.

Using the debugger, I see that the DMA2 Channel 4 while loop always times out and 1-3 HAL_SD_STATE_BUSY, HAL_SD_CARD_RECEIVING, and the flag is not set, respectively. DMA2 Channel 2 works correctly in that 1-3 are HAL_SD_STATE_READY, HAL_SD_CARD_TRANSFER, and the flag is set.

I also used an oscilloscope to probe the SDCLK and SDDA0 lines. When DMA2 Channel 5 is used, I see SDCLK toggling and SDDA0 transmitting or receiving. When DMA2 Channel 4 is used, SDCLK is held high and SDDA0 remains low.

What is happening here? Why does DMA2 Channel 4 not work while DMA2 Channel 5 works for the same setup? I would like to use DMA for both the SDMMC Rx and Tx.

#stm32-l4 #dma-sdmmc #sdmmc #stm-32

[Tesla DeLorean]

Posted on May 04, 2018 at 17:48

Can you link to a web page for an STM32L461VG, Google isn't helping me.

Not sure of the value of two DMA channels in this context the bulk-transfers, and the command stream is serialized in a way that it's either READING or WRITING, and not putting it's pants on both legs at a time.

Would check the RM and errata if there is a specific issue or one channel or the other, but changing things frequently requires changing settings in about half-a-dozen places to make sure you're looking at the right flags, and binding to the right IRQ handler, etc.

[Imen.D]

Posted on May 16, 2018 at 12:01

Hello

simone.agha

,

Can you please precise which CubeMx version and Firmware package are you using ?

I recommend you to checkif you have encountered this issue using the latest version.

Best Regards,

Imen

[Imen.D · Accepted solution]

Posted on May 24, 2018 at 17:59

Hello,

When using DMA2_Channel4 for TX and RX paths, there is no issue.

The problem occurs when using DMA2_Channel4 for one path and DMA2_Channel5 for the other path.

This is due to the fact that two channels are configured for SDMMC1 request.

The SDMMC DMA request is not dependent to a direction (it is SDMMC1 and not SDMMC1_TX or SDMMC1_RX).

So, as a workaround, we suggest to use one of these solutions:

• 1st solution : 

  Use same DMA channel for both Rx and Tx paths.

• 2nd solution : Clear the request of the other path before to perform a DMA transfer;

=> This can be done by using the function LL_DMA_SetPeriphRequest().

Best Regards,

Imen.

[Simone Agha]

Posted on May 29, 2018 at 18:16

Hi Imen,

I used the first solution you described (use the same DMA channel) and that solved my problem.

Thanks!

Simone