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FDCAN Message RAM fixed organization

Marco Stucchi ABB

Hi, I've developed a CAN driver for STM32H7 and greatly appreciated the capability to modulate FIFO buffers elements number and size. I am now porting such a driver to STM32L5 but It looks like this is not possible in the STM32L5, where the FIFOs have a fixed number of 3 elements and a fixed size of 64 bytes. The peripheral is used in this way also from the HAL libraries (stm32l5xx_hal_fdcan.c) by means of defined symbols (e.g. SRAMCAN_RF0_NBR = 3, SRAMCAN_RF0_SIZE = 18 * 4).

I wanted to know if this limitation is just in the HAL library and could be programmed something like the STM32H7, where I can increase the FIFO depth and decrease the element size (e.g. 8 FIFO entries with a maximum payload of 8 bytes).

That would definitely save the day, preventing me from offloading the FIFO from an ISR in order to prevent overflow in the FIFO itself.

To better explain: I'd like to be able to have more smaller entries in the FIFO, instead of 3 entries that could potentially host 64-bytes messages.

The lack of bigger payloads is granted by the system.

Thanks a lot,

Marco Stucchi