Fast UART Receive Interrupt with FIFO mode

[GS1]

Hi all,

I need to install a communication between 2 STM32H743 units (on one board) with maximum speed (10 MBit) on UART mode and I need to check incoming characters to detect Linefeeds etc.

The problem is that with FIFO mode enabled (Threshold 1/8) interrupts for incoming data are not generated after each character. Therefore the linefeeds are not properly detected and the system waits for the end of the record.

When FIFO mode is disabled, everything is working as expected. However then I only can set the speed to 2 MBit. For higher speeds I get overrun errors.    

Is there a means to generate receive-interrrupts for even only 1 character in the FIFO?

[S.Ma]

Not using DMA in cyclic buffer with detection of EOF char if FIFO is incompatible with it?

[GS1]

Thank you for your suggestion.

Bug I have to install a line-by-line communication with handshake (Acknowledge) to continue sending the next line. I need it for a bootload/flash function. Therefore I need a kind of fast detection of LF.

I currently install a fixed block length handshake, but this ends up in sending unneeded characters which I have to discard then. This might eat up the advantage of faster data rate speed.

[S.Ma]

Make a 2048 bytes packet length which will take 1+ msec to transmit and give the same time to process previously received block by DMA. Or like internet, give a number for each packet with possibility of late acknowledge. Using a multi-packet SRAM DMA cyclic buffer, you could just grab and check data using time intervals instead of sequential ACK SEND scheme?

[GS1]

Hi,

The reason why I can not just transmit a huge block and devide it lateron in separate lines is that my PC tool for loading new firmware to my systems is sending one Intel-HEX line to the unit, and expects ana Acknowledge as soon as it is stored / flashed in the target processor. The target-processor however is connected to another STM32H7 which communicates via USB with the PC tool. This processor simply transmits the received data from the PC to the target unit, waits for the Acknowledge from the target and confirms the Acknowledge back again to the PC. So 3 parts are involved in the bootloader process.

Currently I achieved to install the inter-processor-communication (2 x STM32H743) with Asynchronous Block transfer with 10 MBit speed. I installed a block-Interrupt mechanismn for 16 Bytes, so the overhead is not too much. This works, however we still would like to switch to a synchronous USART communication, but there occurs an UDR Underrun error in the Slave USART and - if I deactivate the Underrun error (this is due to the fact that the slave doesn't transmit anything), I get an Overrun error interrupt after the first byte in the block.

A simple test with transmission of a block without Interrupt is working, but I need Interrupt handling of course.

Any ideas?

[S.Ma]

Take a step back as there are some wait timings to program the flash where the next block could be received as dead time. As the data flows indirectly through different mcus, the average.data transmit speed is not just baudrate... If the interface was SPI how woulf you implement it? This might gave some preffered implementation guidance.

[Tesla DeLorean]

Two approaches.

One have a routine that flushes the USART, a while loop on RXNE to empty FIFO. It monitors the character stream as it buffers and flags for a worker task to process the buffer, later.

Have your other interrupts at the same preemption level (including a ticker like SysTick or TIM), and have them call the same routine, same as the USART IRQ. This way you'll always keep the FIFO empty and flag whenever a end-of-line is detected.

Two, have a larger circular DMA buffer, 16-bit words you can mark as harveted, with interrupts at HT/TC (optional), or a TIM at a fraction of the buffer fill rate, to pull the tainted words from the circular buffer, and replacing with a marker word (say 0xFF00) which won't appear in normal traffic.

[GS1]

Yes, you are right: There is dead time inbetween the transmitted lines.

The idea behind switching to USART synchronous mode simply is, that it would be a safer kind of transmission due to the clock output. Asynchronous UART with 10 MBit baudrate is actually a bit risky.

I have two USART ports between the units, so each one has a Master USART and a Slave USART and transmission is done in one direction only on each USART. This allows a kind of handshaking process. On a single SPI this would not be a simple handshake process due to simultanous transmission/reception. Actually this is my next task as I have more processors on the board, which have to be programmed via SPI connection to the Master STM32H7. So this task is next one on my desk.