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Failed to Initialise Ethernet in STM32H7

NOza.2
Associate II

Hello,

We are developing an industrial application based on STM32H7 (STM32H723ZGTx) and we are using NXP "TJA1101B" for PHY.

It is connected to STM32H7 using RMII interface. We took hardware reference from "TJA1100 Customer Evaluation Board" schematic. When we initialise PHY in STM32H7, it failed to initialise PHY (HAL_ETH_Init failed with HAL_ERROR). We are using STM32Cube version 1.9.1.

 

 

PC1 ETH_MDC
PA7 ETH_CRS_DV
PC4 ETH_RXD1
PC5 ETH_RXD0
PA1 ETH_REF_CLK
PB11 ETH_TX_EN
PB13 ETH_TXD1
PB12 ETH_TXD0
PA2 ETH_MDIO
PA6 ETH_EN [Set O/P High]

 

 

Same Ethernet code is working in "NUCLEO-H723ZG" evaluation kit with LAN8747-A. Will you please guide us the debug the issue in hardware of firmware? 

 

Thanks & Regard

Neel 

1 ACCEPTED SOLUTION

Accepted Solutions
NOza.2
Associate II

Hello All,

 

Yesterday, We found the issue. STM32 was not receiving Active clock from TJA1101B PHY.

As per datasheet, TJA1101B must be switched to Normal mode, either autonomously or via an SMI command. We have changed the state using CONFIG1 pin and provided external pull up to drive state high.

 

Thanks & Regards,

Neel 

View solution in original post

8 REPLIES 8
Pavel A.
Evangelist II

> STM32Cube version 1.9.1.

You may want to review and use this example for the current, supported HAL library version.

>When we initialise PHY in STM32H7, it failed to initialise PHY (HAL_ETH_Init failed with HAL_ERROR). 

Please use the debugger and find where exactly HAL_ETH_Init errors out.

The PHY data sheet, p. 6.6, says that the PHY can be set to "autonomous operation" via pin strapping. This is worth to do. Make a delay  ~ 10 ms from power-up to HAL_ETH_Init call, to let the PHY wake up.

STOne-32
ST Employee

Dear @NOza.2 ,

I would suggest to check the difference between both on the 50MHz reference clock from the PHY to the MCU and how it is generated either using a  25MHz crystal or any other 25MHz / 50 MHz clock . 
Hope it helps you.

Cheers,

STOne-32

Hello @Pavel A.,

> Please use the debugger and find where exactly HAL_ETH_Init errors out.

STM32 performs Software reset operation after setting register bit (SWR in ETH_DMAMR). This bit is automatically cleared after the reset operation is complete in all clock domains. The reset operation is complete only when all resets in all active clock domains are deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion.

In our case, this bit (SWR in ETH_DMAMR) is not automatically cleared after setting the register bit. We are waiting 500 msec to check this bit is automatically cleared or not.

 

  /* Ethernet Software reset */
  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
  /* After reset all the registers holds their respective reset values */
  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);

  /* Get tick */
  tickstart = HAL_GetTick();

  /* Wait for software reset */
  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
  {
    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
    {
      /* Set Error Code */
      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
      /* Set State as Error */
      heth->gState = HAL_ETH_STATE_ERROR;
      /* Return Error */
      return HAL_ERROR;
    }
  }
Pavel A.
Evangelist II

50 ms is the default value of ETH_SWRESET_TIMEOUT. What if you wait longer, will the reset bit clear in any reasonable time?  (you can override ETH_SWRESET_TIMEOUT in stm32h7xx_hal_conf.h)

 

LCE
Principal

From RM:

Bit 0 SWR: Software Reset
When this bit is set, the MAC and the DMA controller reset the logic and all internal registers
of the DMA, MTL, and MAC. This bit is automatically cleared after the reset operation is
complete in all clock domains. Before reprogramming any register, a value of zero should be
read in this bit.
Note: The reset operation is complete only when all resets in all active clock domains are
deasserted. Therefore, it is essential that all PHY inputs clocks (applicable for the
selected PHY interface) are present for software reset completion. The time to complete
the software reset operation depends on the frequency of the slowest active clock.

So, as @STOne-32 said: check the hardware clock from PHY.

Apart from that for the following steps, have you compared LAN8742 register addresses and bits with those of the NXP PHY?

mayank
Associate II

Hello @NOza.2 

Did you find a solution?

For us we are using STM32H7 with KSZ8081 and feeding 25MHz clock to Phy which in turn is sending 25MHz clock to STM32H7 and using MCO1 to drive the MAC all using MII. 

We run into same problem with some boards, not all. We have 5-6 different boards, some in HVM but yet same design fails on one particular set of boards.

I built project yesterday using CubeX and it does not cset RCC_AHB1RSTR_ETH1MACRST to clear MAC. 

 

Is that requird? Why do we even want to reset on power on.. ?

NOza.2
Associate II

Hello All,

 

Yesterday, We found the issue. STM32 was not receiving Active clock from TJA1101B PHY.

As per datasheet, TJA1101B must be switched to Normal mode, either autonomously or via an SMI command. We have changed the state using CONFIG1 pin and provided external pull up to drive state high.

 

Thanks & Regards,

Neel 

Dear @NOza.2 ,

All thanks for sharing the information back to the Community. Much appreciated !

Ciao,

STOne-32