Example STM32F4xx_DSP_StdPeriph_Lib_V1.0.0 - TIM - DMA does not work

[flyer31]

Posted on January 31, 2012 at 14:53

Hi,

this example code does not work (I tried on the Keil board, PA10 is there available, so not any conflicts) The PWM frequency comes up with 17.5 kHz, as written in the example code. But the functionality, that the duty cycles changes after 3 repetitions, does not work. It always changes only between the first and the last duty cycle given in the array SRC_BUFFER. And it changes after every cycle - it does not keep the duty cycle constant for 3 repetitions as expected. If I read the Ref Manual for the timer DMA, I would expect that DMA_InitStructure.DMA_PeripheralBaseAddr should be set to the address of TIM1_DMAR, and not directly to TIM1_CCR3. As given, the signal shows some spurios spikes, I think the reason is, that TIM1_CCR3 is addressed here directly. If you change the address to TIM1_DMAR, and invoke the configuration function    TIM_DMAConfig( TIM1, TIM_DMABase_CCR3, 1); , then these spikes are gone (I think it anyway is a clear problem of this example, that TIM_DMAConfig is not invoked - to my understanding this function MUST be invoked to set the TIM1_DCR register). But anyway the example keeps changing the duty cycle after every cycle. Somebody has some hint how to fix this? (ST should ...). I downloaded my STM32F4xx_StdPeriph_Examples yesterday, so all should be up to date.

[Dan Hepler]

Posted on February 05, 2015 at 19:33

I can confirm that ST's example WORKS FINE AS IS. No changes are necessary.

I have tried this example on one of the NUCLEO-F411RE boards, updating the system_stm32f4xx.c file for HSI and PLL to run at 48MHz (arbitrary) because there is no HSE crystal installed on this dev board. Here are some notes: 1. The repetition counter repeats 4 times, not 3 times. This is stated in RM0383: ''If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1).'' 2. The first set of 4 pulses (50% duty) occur twice (2x4=8 times total) because the TIM1 module is already set up for 50% upon first update event, the DMA transfers the 50% duty cycle in again. 3. Using TIM1 DMAR as you stated, works identically as their initial configuration. There is no difference between having the DMA write to the TIM1->CCR3 register directly or using the TIM1->DMAR when configured correctly to use the CCR3 register.

// Add this line to main()
TIM_DMAConfig( TIM1, TIM_DMABase_CCR3, TIM_DMABurstLength_1Transfer );
// Modify this line in TIM_Config()
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&TIM1->DMAR) ;

Happy coding.