Embedded World 2013 - Free Discovery Kits

[Roman LUDIN]

Posted on February 11, 2013 at 09:01

Please note that ST will distribute this year again significant number of variety Discovery kits for free during Embedded World show in Nuremberg, February 26-28. For more details and discovery kit registration link go to:

http://www.st.com/ew2013

There will be a set of life presentations with technical content running every day on ST booth:

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Topic

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Time Slot

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Free emWin GUI library taking the most from newest STM32

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10:00

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Getting started with SPC56 family in few minutes

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11:00

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NFC connectivity and Energy harvesting

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12:00

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Ultra Lower Power applications MCU selection

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13:00

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Code generation for ARM� Cortex-M� from MATLAB� and Simulink�

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14:00

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Embedded Java solution for STM32

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15:00

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Advanced analog for wearable electronics

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16:00

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Getting started with SPC56 family in few minutes

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16:30

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#discovery-kit #stm32

[frankmeyer9]

Posted on February 21, 2013 at 11:24

Forum SW error - double post, again...

[frankmeyer9]

Posted on February 21, 2013 at 11:25

The ARM Cortex-M4 core in ST’s STM32F4 variants is further enhanced with ST’s Adaptive Real-Time (ART) Accelerator. The ART Accelerator achieves zero-wait execution from Flash and achieves 225DMIPS (Dhrystone MIPS) and 606 Coremark (EEMBC Coremark benchmark) scores using industry-standard performance metrics.

Does it have faster Flash, or just adding one or two waitstates more ?

[Tesla DeLorean]

Posted on February 21, 2013 at 13:51

Does it have faster Flash, or just adding one or two waitstates more ?

It's bigger and smaller at the same time, does that help? From my conversations with the FAE the 2MB part is a geometry shrink, using a 70nm process vs the 90nm of the original F4, with a power rating equivalent to the smaller variant. I'm waiting on some samples. I'd expect the silicon to be faster. Flash longevity/reliability usually diminishes with geometry. The ART does a pretty good job of masking the intrinsic slowness of FLASH. As the M3/M4 doesn't have a cache, the ART represents a cache for the part, leveraging prefetching and much wider read-line of the array. I've been reasonably happy with it's effectiveness. A more honest benchmarking approach would be to publish them with/without ART enabled. I'm generally suspicious of synthetic benchmarks, especially when they vary compiler to compiler, and settings. I'd much rather see the CORE as a fixed assembler block to provide some vendor consistency and prevent compiler goosing.

[Tesla DeLorean]

Posted on February 21, 2013 at 13:57

Sorry, I won't be able to make it to Nuremberg next week - can you pop my Discovery board(s) in the post...?

Think of all the money you'll save on travel and lodging, should pay for a couple of boards?

[frankmeyer9]

Posted on February 21, 2013 at 14:52

I'd expect the silicon to be faster. Flash longevity/reliability usually diminishes with geometry.

And generally more susceptible to EMI and radiation.As the M3/M4 doesn't have a cache, the ART represents a cache for the part, leveraging prefetching and much wider read-line of the array. I've been reasonably happy with it's effectiveness. I'm too, basically. An ART-miss is IMHO the same as a Cache page miss, with 'unfortunate' instruction sequences have the same effect. I had compared the ARM FFT bin example both on STM32F4@168MHz, and on a TI LM4F120@40MHz (It's maximal clockrate without waitstates). The F4 was only twice as fast as the LM4F with identical compiler and optimization. Slightly off the 4.2 clocking ratio.I'm generally suspicious of synthetic benchmarks, especially when they vary compiler to compiler, and settings. I'd much rather see the CORE as a fixed assembler block to provide some vendor consistency and prevent compiler goosing. That's true of course. Most benchmark test explicitly allow such compiler tweaking. It gives at least rough numbers to compare MCU/compiler combinations, but never ever relief the designer from thorough evaluation.