ECC implementation for SDRAM in STM32H7

[SMula]

Hi team,

We are working on project where external SDRAM is interfaced with STM32H7 microcontroller through FMC and its working fine.

Now I need to implement ECC for the SDRAM, Can anyone help me out and the process flow to do that and any inbuilt register to be configured for doing ECC or we have to configure additionally?

Microcontroller : STM32H743BIT6

External SDRAM : AS4C4M32SA

Thank you

Shivakumar

[Bouraoui Chemli]

Hi @SMula​ 

Today, there is no hardware support for ECC on SDRAM. It should be managed by software.

Bouraoui

[SMula]

Hi @Bouraoui Chemli​ ,

Thank you for your response.

Can you share your thoughts or any reference documents to implement ECC for external SDRAM. It would be very much helpful as I am new to this concept.

Please guide me to implement ECC.

Thank you

Shivakumar

[Tesla DeLorean]

Perhaps look at documentation and app notes from Intel, Xilinx and other vendors actively using ECC on their external memories. FPGA related IP in this area might be the most readily accessible and documented. In PC memory subsystems the DIMMs are typically 36-bit wide for 32-bit data.

ECC is a complex topic, seek professional training or contractors with expertise if your team or management lack those skills in-house.

[SMula]

Team,

To implement ECC for SDRAM do we need to have any other IC which does ECC operation or it is available in STM32H7 or it should be available in AS4C4M32SA SDRAM IC which we are currently using.

Please provide your inputs so that I get clarity.

Thank you

Shivakumar S M

[SMula]

Team,

The SDRAM IC we are using does not have any ECC registers to correct, but still can we implement the ECC for it. I don't have much idea about it so if anyone knows the answer please post it here.

Thank you

Shivakumar S M

[Tesla DeLorean]

You were already told the STM32H7 does not support ECC on external memories.

It is not a SDRAM level implementation, you either need external logic or the MCU's memory-side bridge chip implements it.

On PC implementations you add a "ninth" chip whose job it to hold the parity, hamming or reed-solomon bits your implementation generates when writing to the memory line, and checks when retrieving it. Subsequent more complex/involved hardware does the correction or flags an error as it processes the data bits from lines that fail the basic test.

For example a 32-bit wide memory lane gets expanded to 36-bit to add the ECC bits. Wider implementations can used, but the STM32 doesn't expose 64-bit data buses..

https://www.tomshardware.com/reviews/ecc-memory-ram-glossary-definition,6013.html

[Tesla DeLorean]

This stuff would typically taught in computer architecture/engineering classes.

Perhaps review topics around parity, hamming-codes, reed-solomon, and related error-correcting codes.

The methods used, and now included, in NAND Flash memories tend to deal with much larger blocks of data.

SDRAM implementations tend to be much more fine-grained as the random-access is done with much smaller units of data.