DTCM and SRAM parallel access

[con3]

Posted on February 08, 2018 at 15:49

Hey everyone,

I'm using a STM32f722ZE.

I wanted to know if I allocate two 32KB buffers. One being in SRAM1 and the other in DTCM, With a double buffer DMA2, can the CPU and DMA run in parallel? To my understanding they can. So as soon as the buffer is filled in SRAM2, the DMA will shift to fill the buffer in DTCM and the CPU can process the data in SRAM2. Then the can sort of do this handshake while avoiding collisions on the bus.

Same thing with AHB1 and AHB2, the DMA2 can access AHB1, while the CPU accesses AHB2, all in parallel?

This is my understanding of the busmatrix. The collisions in requests only occur when the same space in the bus is accessed, i.e. Both targeting AHB1 .

Thanks in advance for any clarification

dtcm stm32f7-dma bus-matrix

[waclawek.jan · Accepted solution]

Posted on February 08, 2018 at 15:53

Yes, that's the point of the bus matrix.

Don't forget, that the CPU needs some RAM not only as buffer for your processes but also for variables and stack. DTCM is fast; I am not sure it's a good idea to move stack out of it for sake of some other process.

JW

[con3]

Posted on February 08, 2018 at 15:54

Perfect, Thanks JW!

Just wanted to be sure I'm not misunderstanding anything

[con3]

Posted on February 08, 2018 at 16:05

Should I just check how much space is reserved in the DTCM for variables and stack or is this a dynamic process that occurs as memory is required?

[Tesla DeLorean]

Posted on February 08, 2018 at 18:15

The value of the DTCM RAM is that it avoids cache coherency issues, so the processor always pulls directly.

To use other SRAM you need to either mark it as uncacheable or invalidate after DMA has changed the content behind the cache.

>>

can the CPU and DMA run in parallel

Ok, to repeat what has been communicated in other threads, contention does not preclude multiple use, operations will be deferred and arbitrated.

Change the mindset from parallel/simultaneously to sequenced/ordered, the hardware is designed to permit concurrent operation in an orderly manner, to the point where you exhaust available bandwidth/channels at which point it will grind along as best it can.

Stacks are best in TCM, but caching should mask slower memories.

[con3]

Posted on February 08, 2018 at 17:31

Or would a buffer in SRAM1 and SRAM2 be better?

[con3]

Posted on February 10, 2018 at 12:26

Hi Clive,

Thank you.

>>

can the CPU and DMA run in parallel

Ok, to repeat what has been communicated in other threads, contention does not preclude multiple use, operations will be deferred and arbitrated.

Change the mindset from parallel/simultaneously to sequenced/ordered, the hardware is designed to permit concurrent operation in an orderly manner, to the point where you exhaust available bandwidth/channels at which point it will grind along as best it can.

This was a bit of a mindset shift, but I completely understand now.

Thanks for all the help thus far!