Posted on February 25, 2014 at 04:02
I use the dma to TX only, the rx is handled in a interrupt with no dma. I've been working on this for quite some time now and I Always get a FEIF6 interrupt.
Specifically I get TC, HT and FE. I dont have really any idea why. I've bindly changed the fiifo params enough that I think I've covered most of them and I still always get FE (every time!!).
What could be causing this, and is there an explination for the fifo params ? Anyone know what they should be ?
/**
* @brief start a dma transfer assuming it has already been inited
*
*
* @note
* @param none
* @retval none
*/
void restartCommDMATX(u8* FrameBuffer,int start, int size)
{
DMA_InitTypeDef DMA_InitStructure;
DMA_DeInit(DMA1_Stream6);
DMA_InitStructure.DMA_Channel = DMA_Channel_4;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&(USART2->DR); // usart2 data register
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)&FrameBuffer[start];
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = size;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
// FIFO
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
// init the dma
DMA_Init(DMA1_Stream6, &DMA_InitStructure);
USART_DMACmd(USART2, USART_DMAReq_Tx, ENABLE);
// setup transfer complete int, and error init
DMA_ITConfig(DMA1_Stream6, DMA_IT_TC, ENABLE);
DMA_ITConfig(DMA1_Stream6, DMA_IT_FE, ENABLE);
DMA_ITConfig(DMA1_Stream6, DMA_IT_TE, ENABLE);
mCommInternalState = STATE_SENDNG;
// start the dma transfer, it will execute now
DMA_Cmd(DMA1_Stream6, ENABLE);
}
