DMA works only first time

brubinstein · ‎2015-03-10

Posted on March 10, 2015 at 22:16

Hi,

I'm using ADC and DMA. For learning purposes no interrupts, just polling LIFR. Staring conversion with ADC_CR2_SWSTART. As soon as TCIF is set, I'm writing 1 to ALL flags to LIFCR (LIFR becomes 0) then re-enabling DMA. Do ADC_CR2_SWSTART again and no more flags in LIFR...EOC flag for ADC is set.

Why is that? What am I missing?

#dma

waclawek.jan · ‎2015-03-10

Posted on March 10, 2015 at 23:52

I don't know ( I never used DMA with ADC), but maybe you might want to try to play with something like a simple timer (*not* the advanced like TIM1/TIM8) or USART. ADC might have its own issues, and/or the bits enabling DMA in the ADC.

Also, look at the DMA registers after the ''restart'', post them here if you want.

JW

brubinstein · ‎2015-03-10

Posted on March 11, 2015 at 01:43

All DMA registers are the same as they were before the first time i.e after init().

DMA after init() first successful Before the next

transfer transfer

LISR 0 0x00000C00 0

HISR 0 0 0

S1CR 0x04002C01 0x04002C00 0x04002C01

S1NDTR 0x4 0 0x04

S1PAR 0x4001224C 0x4001224C 0x4001224C

S1M0AR 0x20000000 0x20000000 0x20000000

S1FCR 0x00000020 0x00000020 0x00000020

ADC3 DMA is looping

SR 0 0x00000010 0x00000012

CR1 0x03000100 0x03000100 0x03000100

CR2 0x00000101 0x00000101 0x00000101

waclawek.jan · ‎2015-03-11

Posted on March 11, 2015 at 09:11

Nice catch, Baruch!

Indeed, the text in ADC chapter contains this:

No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the

ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is

not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.

A hidden bit influencing hardware's behaviour is an, ehm, really bad idea, if you ask me...

Thanks for sharing this info.

JW