DMA on SPI

[Stastny.Petr]

Posted on November 11, 2016 at 14:20

Hello,

I have one question. I have two CPUs (STM32F407 + STM32F103) and I need to ''share'' (or better say ''synchronize'') 64 bytes between these CPUs every 100us. So every 100us the CPU must send 64 bytes to another CPU and also read 64 bytes from the second CPU. Is it possible to do with DMA without any CPU load?Thank youPetr

[waclawek.jan]

Posted on November 11, 2016 at 15:41

That's about 5Mbit/s. Should be doable with SPI, depending on the APB clocks. The devil is, as usually, in the details (e.g. ensuring consistency, in other words, how to prevent the DMA overwrite part of the data with new data while the receiver is processing them; similarly at the transmitter).

JW

[Stastny.Petr]

Posted on November 11, 2016 at 20:53

SPI would be nice, but how to say DMA that there is an array to send? How to declare this array?

[waclawek.jan]

Posted on November 12, 2016 at 12:15

It sounds that you are not very familiar with the concept of DMA, are you.

Basically, DMA channels have registers to set source address (e.g. address in memory of data array to send), destination address (e.g. , number of transfers, and then a control register where among other things (e.g. telling the direction of transfer and size of data in one transfer) you can enable it (that's the ''start''). You might perhaps tell us more about yor application, and meantime read the DMA chapter in the RMs. Note that there are a few differences between DMA in 'F1xx and 'F4xx. Other way (I am not familiar with) is to use some of the ''libraries'' (SPL, Cube); there are examples for DMA-driven SPI transfer out there. JW

[Tesla DeLorean]

Posted on November 12, 2016 at 14:41

How to declare this array?

volatile? From the processors perspective it is just a collection of bytes or words, how you structure the content is up to you. Like C pointers, the DMA is just going to need the start address in memory, and the length/size. The alignment of the memory address should match that of the transfer unit size. Considered using a dual-ported memory? Or some transfer method that doesn't required two areas that can be written by two Processors, and two DMA operations? This doesn't seem at all well thought through.

[Seb]

Posted on December 10, 2016 at 20:00

To be experimented (it is a guess) : Use a u8 TX_RX_Buffer[64]; on both side, the DMA will be in cyclic mode (rolling on this buffer). DMA TX and RX to point on this buffer. Before transferring, put the data to transmit on this buffer, then the master push 64 bytes. Once the 64 bytes are transffered, use NSS rising edge (if available) to generate an EXTI so that the slave SPI backup the received buffer data for future processing.