2014-01-27 02:27 PM
Given an F4 (F405 and F429) or even F2 ..
Is it possible for a DMA to be both MemoryToMemory and have the rate of delivery be set by a timer? ie: I'm effecting a copy from an array in RAM, to a GPIO. (a byte at a time, say, otherwise I could use SPI tricks.) With MemoryToPeripheral I think you can do it, but is M2M full speed only? Or is it possible to refer to a GPIO as a peripheral somehow? Thank you my friends, jeff #stm32f4-dma2014-01-28 11:44 AM
Theres some macros that aren't fond in the .h file referenced; you're also just using src and dst memory buffers, with one as a peripheral. Doesn't seem to work for me when I do that.
How odd :) I think I need to reduce to a very specific test case and try similar..2014-01-29 05:39 AM
> ''Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)'' > --> I'm unclear on 'trigger' term if it means what I think it does.. but this suggests memory to memory rate control as I'd need This probably supposed to read like ''If you set M2M mode (and you can do that on any stream in DMA2), then it is enough to set EN (from software - that's why ''software trigger'') to start the transfer; unlike in M2P/P2M modes, where transfers are initiated from the hardware inputs connected to the peripherals (through the ''channels'' multiplexer)''. > Theres some macros that aren't fond in the .h file referenced Namely? Did you notice that I don't use the stock stm32f4xx.h? > you're also just using src and dst memory buffers, with one as a peripheral. That was the purpose of my experiment, to determine, whether in M2P/P2M modes the DMA insists of having an APB-mapped address, or any other could be used. As the comment says, DMA1 throws an error if both addresses are in SRAM, whereas DMA2 allows it. I would be very surprised if GPIO wouldn't be as good as SRAM as target address. While I like to play, I am not fond of using experiments as replacement for what I expect to be described clearly in the manual. But, given the current state of publicly available documentation, and given that ST's support apparently doesn't want to deal with a petty sub1M consumer I am, sadly, this is the only option left for me. JW2014-01-29 06:55 AM
2014-01-29 08:36 AM
2014-01-29 08:56 AM
Here's an externally clocked example I built a while back. I think I'd just need to change the channel/stream for it to clock from an internal source.
2014-01-29 09:10 AM
> In this case, the M2M mode works to blit from src array to GPIO. The other two modes M2P and P2M do not work.
Specify ''do not work''. Have you looked at the DMA stream and error register content after it ''did not work''? Are you sure you set up correctly the DMA's trigger? Which timer are you using, and to which stream/channel are you feeding it and how? JW2014-01-29 10:18 AM
2014-01-29 01:30 PM
2014-01-29 02:31 PM
DMA_IT_TCIF1
I was using:
DMA_IT_TCIF
As such I was not properly clearing the DMA and I suspect it was hanging.
I am now good, and in debted to you both (again :)
2014-06-11 04:20 PM
Hi,
Thank you very much for posting this example - I'm not exactly sure how to proceed, however. I am building a custom data logging system for my next offroad vehicle that will be used to log accelerometer readings, speed, GPS position, wheel speeds, suspension travel, engine operating parameters, etc. I'm attaching a parallel ATA or CompactFlash (unsure which at this point, though they're logically very very similar) solid state storage unit of approximately 16-64GB size to an STM32F series MCU. Port E is routed to the D0-D15 lines, #IORD/#IOWR to a few GPIO pins (since my fallback if I can't get DMA working is to use PIO mode) and now I'm trying to figure out how I should connect my DMARQ and #DMACK pins to Timer 8 on the STM32F so the DMA controller can handshake with the drive properly. The way P-ATA/CF/IDE DMA handshaking works is that the controller initiates a DMA transfer command by writing command parameters to several registers over the bus, then the storage device requests the first word by activating DMARQ. The microcontroller then needs to respond by driving data onto port E, waiting the setup time, then activating #DMACK and the appropriate #IORD or #IOWR signal (depending on which way the data is flowing... in my case, writing). Once the #DMACK signal activates, the storage device receives or transmits the data, then reactivates DMARQ to request the next transfer as required.I may need to add external glue logic for #IORD/#IOWR, I think. But my major question is - which external signals on Timer 8 do I use as DMARQ/#DMACK so this will all work? Is there any way to do it? Reading the software reference manual and your example cleared things up a bit, but I'm still not really sure what signals I should be using here. Once I know that, I can finish laying out my PCB artwork, build the board, and worry about writing the software if PIO mode ends up being a bottleneck.Again, thank you very much for taking the time to write up that example - it answered many of my questions, just not all of them.