DMA Memory Increment mode overflow

[fausto]

Posted on March 09, 2016 at 16:37

Hi,

I am using the DMA for transfer data from ADC converter to external memory RAM. The DMA is configured in incremental mode so every time that I read data from ADC converter they are stored in a different memory location. I try to be clear: -I read 16 bit of data from the data registre of ADC converter -i ask the DMA to transfer data to the RAM memory -I increment the DMA memory pointer of 2 position (each position represent a 8 bit memory register) All works fine but after writing 2^17 samples , the DMA start writing again from his original value. I haven't find anything in the datasheet about this limitation, anybody know about some sort of shadow register ? Thanks a lot for the help.

DMA2_Stream0->CR&=~(7<<
25
);
DMA2_Stream0->CR|=(0<<
25
); 
DMA2_Stream1->CR&=~(7<<
25
);
DMA2_Stream1->CR|=(2<<
25
); 
DMA2_Stream2->CR&=~(7<<
25
);
DMA2_Stream2->CR|=(1<<
25
);
DMA2_Stream0->CR|=(1<<
13
);
DMA2_Stream0->CR|=(1<<
10
); 
DMA2_Stream1->CR|=(1<<
13
);
DMA2_Stream1->CR|=(1<<
10
); 
DMA2_Stream2->CR|=(1<<
13
); 
DMA2_Stream2->CR|=(1<<
10
); 
DMA2_Stream0->CR&=~(3<<
11
);
DMA2_Stream0->CR|=(1<<
11
); //peripheral data syze imposto a half word(16bit)
DMA2_Stream1->CR&=~(3<<
11
);
DMA2_Stream1->CR|=(1<<
11
); //peripheral data syze imposto a half word(16bit)
DMA2_Stream2->CR&=~(3<<
11
);
DMA2_Stream2->CR|=(1<<
11
); //peripheral data syze imposto a half word(16bit)
DMA2_Stream0->CR|=(0<<
6
);// imposto peripheral to memory transfer
DMA2_Stream1->CR|=(0<<
6
);// imposto peripheral to memory transfer
DMA2_Stream2->CR|=(0<<
6
);// imposto peripheral to memory transfer 
DMA2_Stream0->PAR= (uint32_t)( &(ADC1->DR));
DMA2_Stream1->PAR= (uint32_t)( &(ADC3->DR));
DMA2_Stream2->PAR= (uint32_t)( &(ADC2->DR)); 
DMA2_Stream0->M0AR=INDIRIZZO_SDRAM_ADC1;
DMA2_Stream1->M0AR=INDIRIZZO_SDRAM_ADC3;
DMA2_Stream2->M0AR=INDIRIZZO_SDRAM_ADC2;
DMA2_Stream0->CR|=(1<<
5
);
DMA2_Stream1->CR|=(1<<
5
);
DMA2_Stream2->CR|=(1<<
5
);
DMA2_Stream0->CR|=1; //abilito stream 0
DMA2_Stream1->CR|=1; //abilito stream 1
DMA2_Stream2->CR|=1; //abilito stream 2

#stm32f429zi-dma

[Tesla DeLorean]

Posted on March 09, 2016 at 16:59

All works fine but after writing 2^17 samples , the DMA start writing again from his original value. I haven't find anything in the datasheet about this limitation, anybody know about some sort of shadow register ?

Well the part is documented to have a 16-bit count register, it counts transfer units in bytes, half-words, or words depending on how you have configured it.I also believe the active counter registers are independent of the holding registers, likely to disconnect and simplify the synchronous implementation.This is an STM32F4 or some other STM32 part?

[fausto]

Posted on March 09, 2016 at 18:04

Hi,

first of all thanks for reply. I am using the STM32f429ZI... Yes, the counter register is 16bit, but during the debug I can see that it is resetted two times before the DMA start again from his initial value. I am figuring out that probably there is some sort of shadow register that work with ''full words (32bit)'' because it is resetted after 2^16 ''full words''. I think that the only solution is using the double buffer mode and change manually the destination adress.