Posted on April 30, 2018 at 03:07 I'm using a Nucleo -F722ZE to interface with an FPGA. The instruction and data cache are disabled. I have timer interrupts to set off the DMA at specific times with 128 bytes per transfer. No matter how I set up the DMA, the first byte is not transmitted. It is clear the DMA engine thinks it was because it terminates without error. I'm actually sending 50 blocks of 128 bytes, and there is a glitch transaction on the odd transfers where the first byte should be, but all the even transfers even that is not present.
I have tried byte to byte and word to byte transfers, as well as no burst and 16 or 4 burst. The timing is the same no matter what - I miss the first byte. Is there something I have to do to 'warm up' the FMC before the DMA gets turned on? I would prefer not to initiate a transfer because it would screw up the over all timing.
If anyone has any ideas, I'd love to hear them. I suppose I could try to send 129 bytes so I get 128, but that's just hoping the glitch doesn't get seen by the FPGA. It should just work.
Mike
#dma #fmc #sram
Note: this post was migrated and contained many threaded conversations, some content may be missing.
